SC28L92 Philips Semiconductors, SC28L92 Datasheet - Page 32

• Manufacturer Part Number: SC28L92
• Description: 3.3V-5.0V Dual Universal Asynchronous Receiver/Transmitter DUART
• Manufacturer: Philips Semiconductors

The timer mode generates a square wave
Philips Semiconductors
ACR Auxiliary Control Register
ACR—Auxiliary Control Register
ACR[7]—Baud Rate Generator Set Select
This bit selects one of two sets of baud rates to be generated by the
BRG (see Table 5).
The selected set of rates is available for use by the Channel A and
B receivers and transmitters as described in CSRA and CSRB.
Baud rate generator characteristics are given in Table 6.
ACR[6:4]—Counter/Timer Mode And Clock Source Select
This field selects the operating mode of the counter/timer and its
clock source as shown in Table 7
ACR [3:0]—IP3, IP2, IP1, IP0 Change-of-State Interrupt Enable
This field selects which bits of the input port change register (IPCR)
cause the input change bit in the interrupt status register (ISR [7]) to
be set. If a bit is in the ‘on’ state the setting of the corresponding bit
in the IPCR will also result in the setting of ISR [7], which results in
the generation of an interrupt output if IMR [7] = 1. If a bit is in the
‘off’ state, the setting of that bit in the IPCR has no effect on ISR [7].
NOTE:
IPCR INPUT PORT CHANGE REGISTER
IPCR [7:4]—IP3, IP2, IP1, IP0 Change-of-State
These bits are set when a change-of-state, as defined in the input
port section of this data sheet, occurs at the respective input pins.
They are cleared when the IPCR is read by the CPU. A read of the
IPCR also clears ISR [7], the input change bit in the interrupt status
register. The setting of these bits can be programmed to generate
an interrupt to the CPU.
2000 Jan 21
3.3V–5.0V Dual Universal Asynchronous
Receiver/Transmitter (DUART)
IPCR
Addr
Addr
ACR
0x04
0x04
1 = change
BRG SET
Delta IP3
0 = set 1
1 = set 2
change
Select
0 = no
Bit 7
Bit 7
1 = change
Delta IP3
change
0 = no
BIT 6
BIT 6
Mode and clock sour select
Counter Timer Mode
See table 7
1 = change
Delta IP3
change
0 = no
BIT 5
BIT 5
1 = change
Delta IP3
change
0 = no
BIT 4
BIT 4
32
Table 7. ACR 6:4 field definition
IPCR [3:0]—IP3, IP2, IP1, IP0 Change-of-State
These bits provide the current state of the respective inputs. The
information is unlatched and reflects the state of the input pins at the
time the IPCR is read.
ACR
000
001
010
011
100
101
110
6:4
111
Delta IP3 int
1 = enabled
1 = High
enable
0 = low
0 = off
BIT 3
BIT 3
IP 3
Counter
Counter
Counter
Counter
MODE
Timer
Timer
Timer
Timer
Delta IP3 int
1 = enabled
External (IP2)
TxCA - 1X clock of Channel A transmitter
TxCB - 1X clock of Channel B transmitter
Crystal or external clock (X1/CLK) divided
by 16
External (IP2)
External (IP2) divided by 16
Crystal or external clock (X1/CLK)
Crystal or external clock (X1/CLK) divided
by 16
1 = High
enable
0 = low
0 = off
BIT 2
BIT 2
IP 2
CLOCK SOURCE
Delta IP3 int
1 = enabled
1 = High
enable
0 = low
0 = off
BIT 1
BIT 1
IP 1
Product specification
SC28L92
Delta IP3 int
1 = enabled
1 = High
0 = low
enable
0 = off
BIT 0
BIT 0
IP 0