UCC1858 Unitrode Semiconductor, UCC1858 Datasheet - Page 7

• Manufacturer Part Number: UCC1858
• Description: High Efficiency, High Power Factor Preregulator
• Manufacturer: Unitrode Semiconductor

APPLICATION INFORMATION (cont.)
tion in the low frequency range (e.g. audio), the charge
current should not be allowed to go very low. Minimum
frequency of the controller is programmed by the current
I
ing current. The value of R
mum frequency is given by:
When the converter comes out of the low power mode,
the time taken to restore normal mode operation (return
to nominal or synchronized frequency operation) must be
minimized. Given that the voltage error amplifier re-
sponse is very slow in PFC circuits, the VAO pin change
is not the best indicator of change in load conditions.
UCC3858 provides a solution where the normal mode
can be restored instantaneously when FBM is pulled be-
low 1.5V. A typical interface would involve the output of
the error amplifier of the downstream converter (with
proper buffering and filtering) driving an npn switch that
pulls FBM down to GND. The buffer and filter should en-
sure that the switch is turned on only when the error am-
plifier of downstream converter is saturated high for a
preset duration indicating a droop in output voltage from
increased load. The FBM input can also be permanently
pulled low to disable the frequency foldback mode com-
pletely, while still using the other features of UCC3858.
FBL pin also acts as a chip disable input when it is
brought below 0.5V.
Capacitor Ripple Reduction
For a power system where the PFC boost converter is fol-
lowed by a DC-DC converter stage, there are benefits to
synchronizing the two converters. In addition to the usual
advantages such as noise reduction and stability, proper
synchronization can significantly reduce the ripple cur-
rents in the boost circuit’s output capacitor. Figure 4 helps
illustrate the impact of proper synchronization by showing
a PFC boost converter together with the simplified input
stage of a forward converter. The capacitor current during
a single switching cycle depends on the status of the
MIN
flowing into pin FBM which sets the minimum charg-
Figure 4. Simplified Representation of a
R
FBM
2-Stage PFC Power Supply
3.5
3
f
Smin
1
FBM
C
T
to set the desired mini-
R
T
UDG-97130
(2)
7
switches Q1 and Q2 and is shown in Figure 5. It can be
seen that with a synchronization scheme that maintains
conventional trailing edge modulation on both converters,
the capacitor current ripple is highest. The greatest ripple
current cancellation is attained when the overlap of Q1
off-time and Q2 on-time is maximized. One method of
achieving this is to synchronize the turn-on of the boost
diode (D1) with the turn-on of Q2. This approach implies
that the boost converter’s leading edge is pulse width
modulated while the forward converter is modulated with
traditional trailing edge PWM. The UCC3858 is designed
as a leading edge modulator with easy synchronization to
the downstream converter to facilitate this advantage. Ta-
ble I compares the I
offered by UCC3858 vs. the I
of synchronizing the turn-on of Q1 and Q2 for a 200W
power system with a V
Table I illustrates that the boost capacitor ripple current
can be reduced by about 50% at nominal line and about
30% at high line with the synchronization scheme facili-
tated by the UCC3858. The output capacitance value can
be significantly reduced if its choice is dictated by ripple
D (Q2) Q1/Q2
0.35
0.45
Switch Sync
Trailing-Edge PWM for
both Boost and Buck
V
1.491A 0.835A 1.341A 0.663A 1.024A 0.731A
1.432A 0.93A
IN
Table 1. Effects of Sychronization on
for Synchronization Scheme
Figure 5. Timing Waveforms
= 85V
Boost Capacitor Current
D1/Q2
CBrms
BST
V
Q1/Q2
1.276A 0.664A 0.897A 0.614A
of 385V.
IN
for D1/Q2 synchronization as
CBrms
= 120V
Inverted Switch Sync
Leading-Edge Boost PWM
Trailing-Edge Buck PWM
D1/Q2
for the other extreme
V
Q1/Q2
IN
UCC1858
UCC2858
UCC3858
= 240V
UDG-97131
D1/Q2