IDT72T51546 Integrated Device Technology, IDT72T51546 Datasheet
IDT72T51546
Related parts for IDT72T51546
IDT72T51546 Summary of contents
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... User selectable I/O: 2.5V LVTTL, 1.5V HSTL, 1.8V eHSTL " " " " " Default multi-queue device configurations " " " " " – IDT72T51546 : 1,024 32Q – IDT72T51556 : 2,048 32Q 100% Bus Utilization, Read and Write on every clock cycle " " " " " ...
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... IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits DESCRIPTION: The IDT72T51546/72T51556 multi-queue flow-control devices is a single chip within which anywhere between 1 and 32 discrete FIFO queues can be setup. All queues within the device have a common data input bus, (write port) and a common data output bus, (read port) ...
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... IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits WCLK WEN 8 WRADD Write Control Logic WADEN Write Pointers PAF FSTR 8 General Flag PAFn Monitor FSYNC FXO FXI FF Active Q Flags PAF SI SO Serial SCLK Multi-Queue Program- SENI ming SENO ...
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... IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits PIN CONFIGURATION A1 BALL PAD CORNER A D14 D13 D12 D10 B D15 D16 D11 D9 C D17 D18 D19 D8 D D20 D21 D22 V DDQ E D23 D24 D25 V DDQ F D26 D27 D28 V DDQ ...
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... Also the total size of any given queue must be in increments of 256 x36. For the IDT72T51546 and IDT72T51556 the Total Available Memory is 128 and 256 blocks respectively (a block being 256 x36) ...
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... IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits status flag, “Packet Ready”. The Packet Ready (PR) flag in conjunction with Output Valid (OV) indicates when at least one packet is available to read. When in packet mode the almost empty flag status , provides packet ready flag status for individual queues ...
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... IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits PIN DESCRIPTIONS Symbol & Name I/O TYPE Pin No. BM Bus Matching LVTTL (L14) INPUT D[35:0] Data Input Bus HSTL-LVTTL These are the 36 data input pins. Data is written into the device via these input pins on the rising edge ...
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... IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits PIN DESCRIPTIONS (CONTINUED) Symbol & Name I/O TYPE Pin No. FM (1) Flag Mode HSTL-LVTTL This pin is setup before a master reset and must not toggle during any device operation. The state of the ...
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... IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits PIN DESCRIPTIONS (CONTINUED) Symbol & Name I/O TYPE Pin No. OE Output Enable HSTL-LVTTL The Output enable signal is an Asynchronous signal used to provide three-state control of the multi-queue (M14) INPUT OV Output Valid ...
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... IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits PIN DESCRIPTIONS (CONTINUED) Symbol & Name I/O TYPE Pin No. PKT (1) Packet Mode LVTTL (Continued) INPUT (J14) PR Packet Ready HSTL-LVTTL If packet mode has been selected this flag output provides Packet Ready status of the Queue selected ...
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... IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits PIN DESCRIPTIONS (CONTINUED) Symbol & Name I/O TYPE Pin No. REN HSTL-LVTTL The REN input enables read operations from a selected Queue based on a rising edge of RCLK. Read Enable (T11) INPUT SCLK ...
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... IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits PIN DESCRIPTIONS (CONTINUED) Symbol & Name I/O TYPE Pin No. TRST (2) JTAG Reset LVTTL (Continued) WADEN Write Address HSTL-LVTTL The WADEN input is used in conjunction with WCLK and the WRADD address bus to select a queue to ...
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... IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits PIN NUMBER TABLE Symbol Name I/O TYPE D[35:0] Data Input Bus HSTL-LVTTL D35-J3, D(34-32)-H(3-1), D(31-29)-G(3-1), D(28-26)-F(3-1), D(25-23)-E(3-1), D(22-20)-D(3-1), Din INPUT Q[35:0] Data Output Bus HSTL-LVTTL Q(35,34)-J(15,16), Q(33-31)-H(14-16), Q(30-28)-G(14-16), Q(27-25)-F(14-16), Q(24-22)-E(14-16), Qout OUTPUT V +2.5V Supply Power CC V O/P Rail Voltage Power DDQ GND Ground Pin ...
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... IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits ABSOLUTE MAXIMUM RATINGS Symbol Rating V Terminal Voltage TERM with respect to GND T Storage Temperature STG I DC Output Current OUT NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device ...
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... IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits DC ELECTRICAL CHARACTERISTICS (Commercial 2.5V ± 0.125V 0$C to +70$C;Industrial Symbol Parameter I Input Leakage Current LI I Output Leakage Current LO (3) V Output Logic “1” Voltage Output Logic “0” Voltage, ...
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... IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits HSTL 1.5V AC TEST CONDITIONS Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels NOTE 1.5V±. DDQ EXTENDED HSTL 1.8V AC TEST CONDITIONS Input Pulse Levels Input Rise/Fall Times ...
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... IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits AC ELECTRICAL CHARACTERISTICS (Commercial 2.5V ± 0.15V 0$C to +70$C;Industrial Symbol Parameter f Clock Cycle Frequency (WCLK & RCLK Data Access Time A t Clock Cycle Time CLK t Clock High Time CLKH ...
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... IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits AC ELECTRICAL CHARACTERISTICS (CONTINUED) (Commercial 2.5V ± 0.15V 0$C to +70$C;Industrial Symbol Parameter t RCLK to Echo RCLK Output ERCLK RCLK to Echo REN Output t CLKEN RCLK to PAE Flag Bus to Low-Impedance (2) t PAELZ RCLK to PAE Flag Bus to High-Impedance ...
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... The values of the PAE/PAF offsets is determined by the state of the DF (default) pin during a master reset. For the IDT72T51546/72T51556 devices the default mode will setup 32 queues, each queue being 1024 x36 and 2048 x36 deep respectively. For both devices the value of the PAE/PAF offsets is determined at master reset by the state of the DF input LOW then both the PAE & ...
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... STANDARD MODE OPERATION (PKT = LOW ON MASTER RESET) WRITE QUEUE SELECTION AND WRITE OPERATION (STANDARD MODE) The IDT72T51546/72T51556 multi-queue flow-control devices can be configured maximum of 32 queues into which data can be written via a common write port using the data inputs (Din), write clock (WCLK) and write enable (WEN) ...
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... QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits READ QUEUE SELECTION AND READ OPERATION (STANDARD MODE) The IDT72T51546/72T51556 multi-queue flow-control devices can be configured maximum of 32 queues which data can be read via a common read port using the data outputs (Qout), read clock (RCLK) and read enable (REN) ...
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... IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits Receive Start of Packet (RSOP) and a Receive End of Packet (REOP). The minimum size for a packet is four words (SOP, two words of data and EOP). The almost empty flag bus becomes the “Packet Ready” PR flag bus when the device is configured for packet mode ...
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... IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits TABLE 5 — PACKET MODE VALID BYTE TMOD1 (D33) RMOD1 (Q33) NOTE: Packet Mode is only available when the Input Port and Output Port are 36 bits wide. read port. The multi-queue internal logic increments and decrements a packet counter, which is provided for each queue ...
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... Figure 21, Read Operation and Null Queue Select for diagram. PAFn FLAG BUS OPERATION The IDT72T51546/72T51556 multi-queue flow-control device can be configured for queues, each queue having its own almost full status. An active queue has its flag status output to the discrete flags, FF and PAF, on the write port ...
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... IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits Note, the FF flag will provide status of a newly selected queue two WCLK cycle after queue selection, which is one cycle before data can be written to that queue. This prevents the user from writing data to a queue that is full, (assuming that a queue switch has been made to a queue that is actually full) ...
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... IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits As mentioned, every queue within a multi-queue device has its own almost full status, when a queue is selected on the write port, this status is output via the PAF flag. The PAF flag value for each queue is programmed during multi-queue device programming (along with the number of queues, queue depths and almost empty values) ...
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... IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits TABLE 4 — FLAG OPERATION BOUNDARIES & TIMING Output Valid, OV Flag Boundary I/O Set-Up OV Goes LOW after 1 In36 to out36 (Almost Empty Mode) (Both ports selected for same queue (see note 1 below for timing) ...
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... IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits TABLE 4 — FLAG OPERATION BOUNDARIES & TIMING (CONTINUED) Programmable Almost Empty Flag, PAE Boundary I/O Set-Up in36 to out36 (Both ports selected for same queue when the 1 Word is written in until the boundary is reached) ...
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... Please refer to Figure 32, PAF n Bus – Polled Mode for timing information. PAEn/PRn FLAG BUS OPERATION The IDT72T51546/72T51556 multi-queue flow-control device can be configured for queues, each queue having its own almost empty/ packet ready status. An active queue has its flag status output to the discrete flags, OV, PAE and PR, on the read port ...
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... IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits Quadrants can be selected on consecutive clock cycles, that is the quadrant on the PAEn/PRn bus can change every RCLK cycle. Also, data can be read out of a Queue on the same RCLK rising edge that a quadrant is being selected, the only restriction being that a read queue selection and PAEn/PRn quadrant selection cannot be made on the same RCLK cycle ...
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... IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits ECHO READ CLOCK (ERCLK) The Echo Read Clock output is provided in both HSTL and LVTTL mode, selectable via IOSEL. The ERCLK is a free-running clock output, it will always follow the RCLK input regardless of REN and RADEN. ...
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... IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits BYTE ORDER ON INPUT PORT: BYTE ORDER ON OUTPUT PORT BYTE ORDER ON INPUT PORT: BYTE ORDER ON OUTPUT PORT BYTE ORDER ON INPUT PORT: ...
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... IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits MRS t RSS WEN REN t RSS SENI t RSS FSTR, ESTR t RSS WADEN, RADEN t RSS ID0, ID1, ID2 t RSS OW, IW RSS FM t RSS MAST t RSS PKT t RSS DFM t RSS DF FF ...
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... IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits w-3 WCLK WADEN WEN WRADD Qx FF PAF Active Bus PAF-Qx (5) PRS RCLK REN RADEN t AS RDADD Qx OV PAE Active Bus PAE-Qx (6) r-2 NOTES: 1. For a Partial Reset to be performed on a Queue, that Queue must be selected on both the write and read ports. ...
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... IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits COMMERCIAL AND INDUSTRIAL 35 TEMPERATURE RANGES ...
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... IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits COMMERCIAL AND INDUSTRIAL 36 TEMPERATURE RANGES ...
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... IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits COMMERCIAL AND INDUSTRIAL 37 TEMPERATURE RANGES ...
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... IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits WCLK t ENS WEN RCLK REN Qout Last Word Read Out of Queue OV NOTES has previously been selected on both the write and read ports LOW. 3. The First Word Latency = t + RCLK + t ...
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... IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits COMMERCIAL AND INDUSTRIAL 39 TEMPERATURE RANGES ...
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... IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits COMMERCIAL AND INDUSTRIAL 40 TEMPERATURE RANGES ...
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... IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits *A* *B* RCLK t ENS REN RDADD RADEN Qout (Device 1) OV HIGH-Z (Device 1) OV (Device 2) WCLK WEN WRADD WADEN Din Cycle: *A* Queue 30 of Device 1 is selected for read operations. The OV is currently being driven by Device 2, a queue within device 2 is selected for reads. Device 2 also has control of Qout bus, its Qout outputs are in Low-Impedance ...
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... IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits COMMERCIAL AND INDUSTRIAL 42 TEMPERATURE RANGES ...
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... IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits COMMERCIAL AND INDUSTRIAL 43 TEMPERATURE RANGES ...
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... IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits COMMERCIAL AND INDUSTRIAL 44 TEMPERATURE RANGES ...
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... IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits COMMERCIAL AND INDUSTRIAL 45 TEMPERATURE RANGES ...
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... IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits COMMERCIAL AND INDUSTRIAL 46 TEMPERATURE RANGES ...
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... IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits COMMERCIAL AND INDUSTRIAL 47 TEMPERATURE RANGES ...
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... IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits NULL QUEUE SELECT *A* RCLK t AS 00100000 RDADD t QS RADEN t AS Null-Q REN t A Qout Q1 Wn-4 Q1 Wn-3 OV NOTES: 1. The purpose of the Null queue operation is so that the user can stop reading a block (packet) of data from a queue without filling the 2 stage output pipeline with the next words from that queue ...
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... IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits *A* *B* WCLK WEN WRADD WADEN Din PAF HIGH-Z (Device 1) PAF (Device 2) Cycle: *A* Queue 5 of Device 1 is selected on the write port. A queue within Device 2 had previously been selected. The PAF output of device 1 is High-Impedance. ...
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... IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits *A* *B* RCLK REN HIGH RDADD RADEN HIGH-Z Qout PAE HIGH-Z (Device 1) PAE (Device 2) Cycle: *A* Queue 30 of Device 1 is selected on the read port. A queue within Device 2 had previously been selected. The PAE flag output and the data outputs of device 1 are High-Impedance. ...
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... IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits COMMERCIAL AND INDUSTRIAL 51 TEMPERATURE RANGES ...
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... IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits RCLK Device 1 Quadrant 2 RDADD 001xxx10 t t STS STH ESTR PAEn/ PRn NOTES: 1. Quadrants can be selected on consecutive cycles RCLK cycle that the ESTR is HIGH, the RADEN input must be LOW. ...
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... IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits *A* WCLK WADEN FSTR t ENS WEN WRADD D5Q24 t 100 11000 DS Wp Wp+1 Dn Writes to Previous Q RCLK RADEN ESTR REN RDADD D5Q24 100 11000 Device 5 -Qn ...
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... IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits *A* *B* RCLK RADEN ESTR REN RDADD D0Q31 000 11111 OE t OLZ Qout W X Prev. Q WCLK t t STS STH FSTR WRADD D0 quad4 D0 Q31 ...
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... IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits COMMERCIAL AND INDUSTRIAL 55 TEMPERATURE RANGES ...
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... IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits COMMERCIAL AND INDUSTRIAL 56 TEMPERATURE RANGES ...
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... IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits WCLK WEN D[39:0] D10 D11 RCLK REN Q[39: ERCLK ERCLK EREN NOTES: 1. All read and write operations must have ceased a minimum of 4 WCLK and 4 RCLK cycles before power down is asserted. ...
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... IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits Serial Programming Data Input Serial Enable Data Bus Write Clock Write Enable Write Queue Select Write Address Full Strobe Programmable Almost Full Full Sync1 Full Flag Almost Full Flag ...
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... QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits JTAG INTERFACE Five additional pins (TDI, TDO, TMS, TCK and TRST) are provided to support the JTAG boundary scan interface. The IDT72T51546/72T51556 incorporates the necessary tap controller and modified pad cells to implement the JTAG facility. ...
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... IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits 1 0 Input = TMS NOTES: 1. Five consecutive TCK cycles with TMS = 1 will reset the TAP. 2. TAP controller does not automatically reset upon power-up. The user must provide a reset to the TAP controller (either by TRST or TMS). ...
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... TAP in response to the IDCODE instruction. IDT JEDEC ID number is 0xB3. This translates to 0x33 when the parity is dropped in the 11-bit Manufacturer ID field. For the IDT72T51546/72T51556, the Part Number field contains the following values: Device Part# Field (HEX) ...
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... IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits HIGH-IMPEDANCE The optional High-Impedance instruction sets all outputs (including two-state as well as three-state types disabled (high-impedance) state and selects the one-bit bypass register to be connected between TDI and TDO. ...
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... IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES (32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits t 1 TCK t 3 TDI/ TMS TDO t 6 TRST t 5 SYSTEM INTERFACE PARAMETERS Parameter Symbol Test Conditions Data Output t DO (1) Data Output Hold t DOH (1) Data Input rise=3ns fall=3ns NOTE: 1 ...
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ORDERING INFORMATION IDT XXXXX X XX Device Type Power Speed NOTE: 1. Industrial temperature range product for the 6ns is available as a standard device. All other speed grades available by special order. DATASHEET DOCUMENT HISTORY 06/06/2003 pgs. 1 through ...