IDT72T51546 Integrated Device Technology, IDT72T51546 Datasheet - Page 34
IDT72T51546
Manufacturer Part Number
IDT72T51546
Description
2.5v Multi-queue Flow-control Devices 32 Queues 36 Bit Wide Configuration 1,179,648 Bits And 2,359,296 Bits
Manufacturer
Integrated Device Technology
Datasheet
1.IDT72T51546.pdf
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NOTES:
1. For a Partial Reset to be performed on a Queue, that Queue must be selected on both the write and read ports.
2. The queue must be selected a minimum of 3 clock cycles before the Partial Reset takes place, on both the write and read ports.
3. The Partial Reset must be LOW for a minimum of 1 WCLK and 1 RCLK cycle.
4. Writing or Reading to the queue (or a queue change) cannot occur until a minimum of 3 clock cycles after the Partial Reset has gone HIGH, on both the write and read ports.
5. The PAF flag output for Qx on the PAFn flag bus may update one cycle later than the active PAF flag.
6. The PAE flag output for Qx on the PAEn flag bus may update one cycle later than the active PAE flag.
Serial Enable
IDT72T51546/72T51556 2.5V, MULTI-QUEUE FLOW-CONTROL DEVICES
(32 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648 and 2,359,296 bits
Serial Input
Serial Clock
Default Mode
DFM = 0
Master Reset
Active Bus
Active Bus
PAE-Qx
PAF-Qx
WADEN
RDADD
WRADD
RADEN
WCLK
RCLK
PRS
WEN
REN
PAF
PAE
OV
FF
(5)
(6)
SENI
SI
DFM
t
t
QS
AS
t
AS
t
QS
Qx
MQ1
w-3
SCLK
Qx
r-2
t
QH
t
MRS
AH
SENO
t
QH
t
SO
AH
Figure 7. Serial Port Connection for Serial Programming
w-2
r-1
SENI
t
SI
ENS
DFM
t
ENS
Figure 6. Partial Reset
MQ2
SCLK
w-1
r
MRS
t
PRSS
t
SENO
PRSS
34
SO
w
r+1
t
PRSH
t
PRSH
w+1
r+2
t
SENI
WFF
SI
DFM
MQn
w+2
SCLK
COMMERCIAL AND INDUSTRIAL
r+3
t
t
MRS
ENS
WAF
SENO
t
t
RAE
ROV
t
ENS
SO
TEMPERATURE RANGES
w+3
r+4
5998 drw12
t
PAF
Serial Loading
Complete
t
PAE
5998 drw11
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