IDT72V3684 Integrated Device Technology, IDT72V3684 Datasheet - Page 14

• Manufacturer Part Number: IDT72V3684
• Description: 16 K X 36 X 2 Syncbififo, 3.3v
• Manufacturer: Integrated Device Technology

diagrams together with Bus-Matching and Endian select operations can be
found in Figures 8 through 13.
SYNCHRONIZED FIFO FLAGS
stages. This is done to improve flag-signal reliability by reducing the probability
of metastable events when CLKA and CLKB operate asynchronously to one
another. EFA/ORA, AEA, FFA/IRA, and AFA are synchronized to CLKA.
EFB/ORB, AEB, FFB/IRB, and AFB are synchronized to CLKB. Tables 4 and
5 show the relationship of each port flag to FIFO1 and FIFO2.
EMPTY/OUTPUT READY FLAGS (EFA/ORA, EFB/ORB)
ORB) function is selected. When the Output-Ready flag is HIGH, new data is
present in the FIFO output register. When the Output Ready flag is LOW, the
previous data word is present in the FIFO output register and attempted FIFO
reads are ignored.
When the Empty Flag is HIGH, data is available in the FIFO’s RAM memory
for reading to the output register. When the Empty Flag is LOW, the previous
data word is present in the FIFO output register and attempted FIFO reads are
ignored.
that reads data from its array. For both the FWFT and IDT Standard modes,
the FIFO read pointer is incremented each time a new word is clocked to its
output register. The state machine that controls an Output Ready flag monitors
a write pointer and read pointer comparator that indicates when the FIFO
memory status is empty, empty+1, or empty+2.
to the FIFO output register in a minimum of three cycles of the Output Ready
flag synchronizing clock. Therefore, an Output Ready flag is LOW if a word
in memory is the next data to be sent to the FlFO output register and three cycles
of the port Clock that reads data from the FIFO have not elapsed since the time
the word was written. The Output Ready flag of the FIFO remains LOW until
the third LOW-to-HIGH transition of the synchronizing clock occurs, simulta-
neously forcing the Output Ready flag HIGH and shifting the word to the FIFO
output register.
Flag will indicate the presence of data available for reading in a minimum of
two cycles of the Empty Flag synchronizing clock. Therefore, an Empty Flag
is LOW if a word in memory is the next data to be sent to the FlFO output register
and two cycles of the port Clock that reads data from the FIFO have not elapsed
since the time the word was written. The Empty Flag of the FIFO remains LOW
until the second LOW-to-HIGH transition of the synchronizing clock occurs,
forcing the Empty Flag HIGH; only then can data be read.
clock begins the first synchronization cycle of a write if the clock transition occurs
at time t
can be the first synchronization cycle (see Figures 15, 16, 17, and 18).
FULL/INPUT READY FLAGS (FFA/IRA, FFB/IRB)
function is selected. In IDT Standard mode, the Full Flag (FFA and FFB)
function is selected. For both timing modes, when the Full/Input Ready flag is
HIGH, a memory location is free in the FIFO to receive new data. No memory
locations are free when the Full/Input Ready flag is LOW and attempted writes
to the FIFO are ignored.
IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFO
BUS-MATCHING 16,384 x 36 x 2, 32,768 x 36 x 2 and 65, 536 x 36 x 2
Each FIFO is synchronized to its port clock through at least two flip-flop
These are dual purpose flags. In the FWFT mode, the Output Ready (ORA,
In the IDT Standard mode, the Empty Flag (EFA, EFB) function is selected.
The Empty/Output Ready flag of a FIFO is synchronized to the port clock
In FWFT mode, from the time a word is written to a FIFO, it can be shifted
In IDT Standard mode, from the time a word is written to a FIFO, the Empty
A LOW-to-HIGH transition on an Empty/Output Ready flag synchronizing
This is a dual purpose flag. In FWFT mode, the Input Ready (IRA and IRB)
SKEW1
or greater after the write. Otherwise, the subsequent clock cycle
TM
WITH
14
writes data to its array. For both FWFT and IDT Standard modes, each time
a word is written to a FIFO, its write pointer is incremented. The state machine
that controls a Full/Input Ready flag monitors a write pointer and read pointer
comparator that indicates when the FlFO memory status is full, full-1, or full-
2. From the time a word is read from a FIFO, its previous memory location is
ready to be written to in a minimum of two cycles of the Full/Input Ready flag
synchronizing clock. Therefore, an Full/Input Ready flag is LOW if less than
two cycles of the Full/Input Ready flag synchronizing clock have elapsed since
the next memory write location has been read. The second LOW-to-HIGH
transition on the Full/Input Ready flag synchronizing clock after the read sets
the Full/Input Ready flag HIGH.
begins the first synchronization cycle of a read if the clock transition occurs at
time t
can be the first synchronization cycle (see Figures 19, 20, 21, and 22).
ALMOST-EMPTY FLAGS (AEA, AEB)
data from its array. The state machine that controls an Almost-Empty flag
monitors a write pointer and read pointer comparator that indicates when the
FIFO memory status is almost-empty, almost-empty+1, or almost-empty+2.
The almost-empty state is defined by the contents of register X1 for AEB and
register X2 for AEA. These registers are loaded with preset values during a
FIFO reset, programmed from Port A, or programmed serially (see Almost-
Empty flag and Almost-Full flag offset programming section). An Almost-
Empty flag is LOW when its FIFO contains X or less words and is HIGH when
its FIFO contains (X+1) or more words. A data word present in the FIFO output
register has been read from memory.
are required after a FIFO write for its Almost-Empty flag to reflect the new level
of fill. Therefore, the Almost-Full flag of a FIFO containing (X+1) or more words
remains LOW if two cycles of its synchronizing clock have not elapsed since
the write that filled the memory to the (X+1) level. An Almost-Empty flag is set
HIGH by the second LOW-to-HIGH transition of its synchronizing clock after
the FIFO write that fills memory to the (X+1) level. A LOW-to-HIGH transition
of an Almost-Empty flag synchronizing clock begins the first synchronization
cycle if it occurs at time t
(X+1) words. Otherwise, the subsequent synchronizing clock cycle may be
the first synchronization cycle. (See Figure 23 and 24).
ALMOST-FULL FLAGS (AFA, AFB)
data to its array. The state machine that controls an Almost-Full flag monitors
a write pointer and read pointer comparator that indicates when the FIFO
memory status is almost-full, almost-full-1, or almost-full-2. The almost-full state
is defined by the contents of register Y1 for AFA and register Y2 for AFB. These
registers are loaded with preset values during a FlFO reset, programmed from
Port A, or programmed serially (see Almost-Empty flag and Almost-Full flag
offset programming section). An Almost-Full flag is LOW when the number of
words in its FIFO is greater than or equal to (16,384-Y), (32,768-Y), or
(65,536-Y) for the IDT72V3684, IDT72V3694, or IDT72V36104 respec-
tively. An Almost-Full flag is HIGH when the number of words in its FIFO is
less than or equal to [16,384-(Y+1)], [32,768-(Y+1)], or [65,536-(Y+1)] for
the IDT72V3684, IDT72V3694, or IDT72V36104 respectively. Note that a
data word present in the FIFO output register has been read from memory.
The Full/Input Ready flag of a FlFO is synchronized to the port clock that
A LOW-to-HIGH transition on a Full/Input Ready flag synchronizing clock
The Almost-Empty flag of a FIFO is synchronized to the port clock that reads
Two LOW-to-HIGH transitions of the Almost-Empty flag synchronizing clock
The Almost-Full flag of a FIFO is synchronized to the port clock that writes
SKEW1
or greater after the read. Otherwise, the subsequent clock cycle
SKEW2
COMMERCIAL TEMPERATURE RANGE
or greater after the write that fills the FIFO to