IDT72V3684 Integrated Device Technology, IDT72V3684 Datasheet - Page 23

• Manufacturer Part Number: IDT72V3684
• Description: 16 K X 36 X 2 Syncbififo, 3.3v
• Manufacturer: Integrated Device Technology

NOTES:
1. t
2. If Port B size is word or byte, ORB is set LOW by the last word or byte read from FIFO1, respectively.
IDT72V3684/72V3694/72V36104 3.3V CMOS SyncBiFIFO
BUS-MATCHING 16,384 x 36 x 2, 32,768 x 36 x 2, 65 and 536 x 36 x 2
B0-B35
A0-A35
If the time between the rising CLKA edge and rising CLKB edge is less than t
cycle later than shown.
SKEW1
CLKA
CLKB
W/RB
WRA
MBB
MBA
ORB
CSA
ENA
ENB
CSB
IRA
is the minimum time between a rising CLKA edge and a rising CLKB edge for ORB to transition HIGH and to clock the next word to the FIFO1 output register in three CLKB cycles.
FIFO1 Empty
HIGH
HIGH
LOW
HIGH
LOW
LOW
t
t
ENS2
ENS2
Figure 15. ORB Flag Timing and First Data Word Fall Through when FIFO1 is Empty (FWFT Mode)
t
DS
W1
Old Data in FIFO1 Output Register
t
SKEW1
t
ENH
t
t
ENH
DH
(1)
t
CLKH
1
t
CLK
t
CLKL
SKEW1
TM
, then the transition of ORB HIGH and load of the first word to the output register may occur one CLKB
WITH
23
2
t
CLKH
t
CLK
t
CLKL
t
3
REF
t
A
t
ENS2
COMMERCIAL TEMPERATURE RANGE
t
REF
t
ENH
W1
4677 drw17