IDT70V28L Integrated Device Technology, IDT70V28L Datasheet - Page 11

• Manufacturer Part Number: IDT70V28L
• Description: High-speed 3.3v 64k X 16 Dual-port Static Ram
• Manufacturer: Integrated Device Technology

DATA
NOTES:
1. To ensure that the earlier of the two ports wins. t
2. CE
3. OE = V
4. If M/S = V
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
NOTES:
1. t
2. BUSY is asserted on port "B" blocking R/W
3. t
DATA
IDT70V28L
High-Speed 3.3V 64K x 16 Dual-Port Static RAM
ADDR
ADDR
WH
WB
BUSY
L
R/W
OUT "B"
must be met for both BUSY input (SLAVE) and output (MASTER).
is only for the 'slave' version.
= CE
IN "A"
IL
"A"
"A"
"B"
"B"
for the reading port.
R
IL
= V
(slave), BUSY is an input. Then for this example BUSY
IL,
refer to Chip Enable Truth Table.
t
APS
(1)
BUSY
R/W
R/W
"A"
"B"
"B"
"B"
, until BUSY
APS
is ignored for M/S = V
"B"
goes HIGH.
t
WB
"A"
(3)
t
= V
BAA
BUSY
IH
IL
and BUSY
(SLAVE).
MATCH
t
WC
11
t
WP
(2)
"B"
input is shown above.
t
WP
S
Industrial and Commercial Temperature Ranges
MATCH
t
DW
t
WDD
VALID
t
WH
BUSY
(1)
4849 drw 12
t
DDD
(3)
t
BDA
t
S
DH
4849 drw 11
t
BDD
VALID