FAN6520B Fairchild Semiconductor, FAN6520B Datasheet - Page 7

• Manufacturer Part Number: FAN6520B
• Description: Single Synchronous Buck PWM Controller
• Manufacturer: Fairchild Semiconductor

FAN6520B Rev. 1.0.3
Figure 5 shows the circuit traces that require additional
layout consideration. Use single point and ground plane
construction for the circuits shown. Minimize any leakage
current paths on the COMP pin and locate the resistor,
R
decoupling between VCC and GND pins. Locate the
capacitor, CBOOT as close as practical to the BOOT and
PHASE pins. All components used for feedback compen-
sation should be located as close to the IC as practical.
Feedback Compensation
Figure 6 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(V
error amplifier (Error Amp) output (V
with the oscillator (OSC) triangular wave to provide a
pulse-width modulated (PWM) wave with an amplitude of
V
output LC filter (L
The modulator transfer function is the small-signal trans-
fer function of V
a DC Gain and the output filter (L
double pole break frequency at F
The DC Gain of the modulator is simply the input voltage
(V
The following equations define the modulator break fre-
quencies as a function of the output LC filter:
Figure 5. PC Board Small Signal Layout Guidelines
V
IN
PULLUP
OUT
IN
OSC
FAN6520B
at the SW node. The PWM wave is smoothed by the
) divided by the peak-to-peak oscillator voltage
F
F
) is regulated to the reference voltage level. The
ESR
LC
.
=
close to the COMP pin. Provide local VCC
=
------------------------ -
2
------------------------------------
2
OUT
1
L C
OUT
ESR C
/V
D
1
BOOT
SW
VCC
GND
BOOT
COMP
and C
. This function is dominated by
OUT
C
C
VCC
+5V
).
BOOT
LC
OUT
and a zero at F
Vin
Q1
Q2
and C
E/A
L
) is compared
C
OUT
OUT
OUT
+V
), with a
OUT
ESR
(16)
(15)
.
7
1.
The compensation network consists of the error
amplifier (internal to the FAN6520B) and the imped-
ance networks Z
pensation network is to provide a closed loop
transfer function with the highest 0dB crossing fre-
quency (F
margin is the difference between the closed loop
phase at F
below relate the compensation network’s poles,
zeros and gain to the components (R1, R2, R3, C1,
C2, and C3) in Figure 6.
F
F
F
F
P2
Z1
P1
Z2
=
=
=
=
Converter Compensation Design
--------------------- -
2 R
---------------------------------------- -
2 R
--------------------- -
2 R
--------------------------------------- -
2 C
Figure 6. Voltage Mode Buck
COMP
COMP
0dB
1
1
OSC
ERROR
AMP
0dB
2
2
3
3
DETAILED COMPENSATION
C
C
PWM
) and adequate phase margin. Phase
R
------------------- -
C
C1
1
1
1
3
C
ERROR
AMP
1
1
and 180 degrees. The equations
Z
1
IN
+
+
C
FB
Z
COMPONENTS
C
R
FB
R2
and Z
2
FB
3
2
C2
0.8V
FB
+5V
FB
0.8V
. The goal of the com-
C3
VIN
SW
Q2
R1
Z
R3
IN
L
Z
C
OUT
IN
OUT
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+V
OUT
V
OUT
(17)
(18)
(19)
(20)