ICL-7107 Intersil, ICL-7107 Datasheet - Page 9

• Manufacturer Part Number: ICL-7107
• Description: 31/2 Digit/ LCD/LED Display/ A/D Converters
• Manufacturer: Intersil

System Timing
Figure 9 shows the clocking arrangement used in the
ICL7106 and ICL7107. Two basic clocking arrangements
can be used:
The oscillator frequency is divided by four before it clocks the
decade counters. It is then further divided to form the three
convert-cycle phases. These are signal integrate (1000
counts), reference de-integrate (0 to 2000 counts) and
auto-zero (1000 to 3000 counts). For signals less than full
scale, auto-zero gets the unused portion of reference
de-integrate. This makes a complete measure cycle of 4,000
counts (16,000 clock pulses) independent of input voltage.
For three readings/second, an oscillator frequency of 48kHz
would be used.
To achieve maximum rejection of 60Hz pickup, the signal
integrate cycle should be a multiple of 60Hz. Oscillator
frequencies of 240kHz, 120kHz, 80kHz, 60kHz, 48kHz,
40kHz, 33
tion, Oscillator frequencies of 200kHz, 100kHz, 66
50kHz, 40kHz, etc. would be suitable. Note that 40kHz (2.5
readings/second) will reject both 50Hz and 60Hz (also
400Hz and 440Hz).
1. Figure 9A. An external oscillator connected to pin 40.
2. Figure 9B. An R-C oscillator using all three pins.
†
ONE INVERTER SHOWN FOR CLARITY
THREE INVERTERS
TYPICAL SEGMENT OUTPUT
1
/
DIGITAL GROUND
3
kHz, etc. should be selected. For 50Hz rejec-
0.5mA
8mA
V+
SEGMENT
TO
OSC 1
ICL7106, ICL7107, ICL7106S, ICL7107S
FROM COMPARATOR OUTPUT
40
FIGURE 8. ICL7107 DIGITAL SECTION
†
TO SWITCH DRIVERS
OSC 2
V+
CLOCK
2
39
/
COUNTER
3
kHz,
1000’s
OSC 3
b
a
9
COUNTER
SEGMENT
DECODE
38
e
40
40
100’s
GND ICL7107
TEST ICL7106
f
7
d
g
a
4
INTERNAL TO PART
INTERNAL TO PART
c
LATCH
b
c
SEGMENT
COUNTER
DECODE
e
FIGURE 9. CLOCK CIRCUITS
10’s
f
7
d
g
LOGIC CONTROL
a
39
39
R
c
b
FIGURE 9A.
FIGURE 9B.
SEGMENT
COUNTER
DECODE
e
f
1’s
7
d
g
a
c
b
38
38
C
500
RC OSCILLATOR
4
37
27
4
1
V+
TEST
DIGITAL
GROUND
CLOCK
CLOCK