TDA19989 NXP Semiconductors, TDA19989 Datasheet - Page 46

• Manufacturer Part Number: TDA19989
• Description: 150 MHz pixel rate HDMI 1.3 transmitter
• Manufacturer: NXP Semiconductors

www.DataSheet.in
NXP Semiconductors
21. Figures
Fig 1.
Fig 2.
Fig 3.
Fig 4.
Fig 5.
Fig 6.
Fig 7.
Fig 8.
Fig 9.
Fig 10. Pixel encoding YCbCr 4 : 2 : 2 ITU656-like
Fig 11. Pixel encoding YCbCr 4 : 2 : 2 semi-planar
Fig 12. Pixel encoding YCbCr 4 : 2 : 2 semi-planar
Fig 13. I
Fig 14. Audio input swap to I
Fig 15. Receiver sensitivity detection . . . . . . . . . . . . . . .24
Fig 16. Modules involved in CEC clock calibration
Fig 17. I
Fig 18. Set-up and hold time definition diagram for
Fig 19. Set-up and hold time definition diagram for
Fig 20. Connecting TDA19989 transmitter using
Fig 21. Connecting TDA19989 transmitter using
Fig 22. Package outline SOT962-3 (TFBGA64) . . . . . . .40
TDA19989_1
Preliminary data sheet
TDA19989 high-level block diagram . . . . . . . . . . .2
TDA19989 Block diagram . . . . . . . . . . . . . . . . . . .4
Pin configuration (TFBGA64). . . . . . . . . . . . . . . . .5
Internal assignment of VP[23:0]. . . . . . . . . . . . . . .8
Pixel encoding RGB 4 : 4 : 4 external
synchronization input (rising edge) . . . . . . . . . . .13
Pixel encoding YCbCr 4 : 4 : 4 external
synchronization input (rising edge) . . . . . . . . . . .14
Pixel encoding YCbCr 4 : 2 : 2 ITU656-like
external synchronization input (rising edge) . . . .14
Pixel encoding YCbCr 4 : 2 : 2 ITU656-like
external synchronization input (double edge) . . .15
Pixel encoding YCbCr 4 : 2 : 2 ITU656-like
embedded synchronization input (rising edge) . .16
embedded synchronization input (double edge) .16
external input synchronization (rising edge) . . . .17
embedded synchronization input (rising edge) . .18
S/PDIF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
single-edge clock mode . . . . . . . . . . . . . . . . . . . .38
double-edge clock mode . . . . . . . . . . . . . . . . . . .38
external clock source . . . . . . . . . . . . . . . . . . . . . .39
internal FRO for CEC. . . . . . . . . . . . . . . . . . . . . .39
2
2
S-bus formats . . . . . . . . . . . . . . . . . . . . . . . . . .21
C-bus access. . . . . . . . . . . . . . . . . . . . . . . . . . .29
2
S-bus channel 0 or
Rev. 01 — 15 February 2010
HDMI 1.3 transmitter with HDCP and CEC support
TDA19989
© NXP B.V. 2010. All rights reserved.
continued >>
46 of 47