MCP2510-EP Microchip Technology, MCP2510-EP Datasheet - Page 46

• Manufacturer Part Number: MCP2510-EP
• Description: Stand-Alone CAN Controller with SPI Interface
• Manufacturer: Microchip Technology

MCP2510
7.6
When the error interrupt is enabled (CANINTE.ERRIE
= 1) an interrupt is generated on the INT pin if an over-
flow condition occurs or if the error state of transmitter
or receiver has changed. The Error Flag Register
(EFLG) will indicate one of the following conditions.
7.6.1
An overflow condition occurs when the MAB has assem-
bled a valid received message (the message meets the
criteria of the acceptance filters) and the receive buffer
associated with the filter is not available for loading of a
new message. The associated EFLG.RX
be set to indicate the overflow condition. This bit must be
cleared by the MCU.
7.6.2
The receive error counter has reached the MCU warn-
ing limit of 96.
7.6.3
The transmit error counter has reached the MCU warn-
ing limit of 96.
REGISTER 7-1: CANINTE - Interrupt Enable Register (ADDRESS: 2Bh)
DS21291C-page 46
bit 7:
bit 6:
bit 5:
bit 4:
bit 3:
bit 2:
bit 1:
bit 0:
MERRE WAKIE ERRIE
bit 7
R/W-0
Error Interrupt
RECEIVER OVERFLOW
RECEIVER WARNING
TRANSMITTER WARNING
MERRE: Message Error Interrupt Enable
0 = Disabled
1 = Interrupt on error during message reception or transmission
WAKIE: Wakeup Interrupt Enable
0 = Disabled
1 = Interrupt on CAN bus activity
ERRIE: Error Interrupt Enable (multiple sources in EFLG register)
0 = Disabled
1 = Interrupt on EFLG error condition change
TX2IE: Transmit Buffer 2 Empty Interrupt Enable
0 = Disabled
1 = Interrupt on TXB2 becoming empty
TX1IE: Transmit Buffer 1 Empty Interrupt Enable
0 = Disabled
1 = Interrupt on TXB1 becoming empty
TX0IE: Transmit Buffer 0 Empty Interrupt Enable
0 = Disabled
1 = Interrupt on TXB0 becoming empty
RX1IE: Receive Buffer 1 Full Interrupt Enable
0 = Disabled
1 = Interrupt when message received in RXB1
RX0IE: Receive Buffer 0 Full Interrupt Enable
0 = Disabled
1 = Interrupt when message received in RXB0
R/W-0
R/W-0
R/W-0
TX2IE
N
R/W-0
TX1IE
OVR bit will
Preliminary
R/W-0
TX0IE
RX1IE
R/W-0
7.6.4
The receive error counter has exceeded the error- pas-
sive limit of 127 and the device has gone to error- pas-
sive state.
7.6.5
The transmit error counter has exceeded the error-
passive limit of 127 and the device has gone to error-
passive state.
7.6.6
The transmit error counter has exceeded 255 and the
device has gone to bus-off state.
7.7
Interrupts are directly associated with one or more sta-
tus flags in the CANINTF register. Interrupts are pend-
ing as long as one of the flags is set. Once an interrupt
flag is set by the device, the flag can not be reset by the
MCU until the interrupt condition is removed.
RX0IE
R/W-0
RECEIVER ERROR-PASSIVE
TRANSMITTER ERROR-PASSIVE
BUS-OFF
Interrupt Acknowledge
bit 0
R = Readable bit
W = Writable bit
C = Bit can be cleared by
U = Unimplemented -
- n = Value at POR reset
MCU but not set
reads as ‘0’
1999 Microchip Technology Inc.