74F191SJ Fairchild Semiconductor, 74F191SJ Datasheet - Page 2

• Manufacturer Part Number: 74F191SJ
• Description: IC COUNTER BINARY UP/DWN 16SOP
• Manufacturer: Fairchild Semiconductor
• Series: 74Fr

Specifications of 74F191SJ

• Logic Type: Binary Counter
• Direction: Up, Down
• Number Of Elements: 1
• Number Of Bits Per Element: 4
• Timing: Synchronous
• Count Rate: 100MHz
• Trigger Type: Positive Edge
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (5.3mm Width), 16-SO, 16-SOEIIJ
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Reset: -

©1988 Fairchild Semiconductor Corporation
74F191 Rev. 1.0.2
Unit Loading/Fan Out
Functional Description
The 74F191 is a synchronous up/down 4-bit binary
counter. It contains four edge-triggered flip-flops, with
internal gating and steering logic to provide individual
preset, count-up and count-down operations.
Each circuit has an asynchronous parallel load capability
permitting the counter to be preset to any desired num-
ber. When the Parallel Load (PL) input is LOW, informa-
tion present on the Parallel Data inputs (P
into the counter and appears on the Q outputs. This
operation overrides the counting functions, as indicated
in the Mode Select Table.
A HIGH signal on the CE input inhibits counting. When
CE is LOW, internal state changes are initiated synchro-
nously by the LOW-to-HIGH transition of the clock input.
The direction of counting is determined by the U/D input
signal, as indicated in the Mode Select Table. CE and
U/D can be changed with the clock in either state, pro-
vided only that the recommended setup and hold times
are observed.
Two types of outputs are provided as overflow/underflow
indicators. The Terminal Count (TC) output is normally
LOW and goes HIGH when a circuit reaches zero in the
count-down mode or reaches 15 in the count-up mode.
The TC output will then remain HIGH until a state
change occurs, whether by counting or presetting or until
U/D is changed. The TC output should not be used as a
clock signal because it is subject to decoding spikes.
The TC signal is also used internally to enable the Ripple
Clock (RC) output. The RC output is normally HIGH.
When CE is LOW and TC is HIGH, the RC output will go
LOW when the clock next goes LOW and will stay LOW
until the clock goes HIGH again. This feature simplifies
CE
CP
P
PL
U/D
Q
RC
TC
0
0
–P
–Q
Pin Names
3
3
Count Enable Input (Active LOW)
Clock Pulse Input (Active Rising Edge)
Parallel Data Inputs
Asynchronous Parallel Load Input (Active LOW)
Up/Down Count Control Input
Flip-Flop Outputs
Ripple Clock Output (Active LOW)
Terminal Count Output (Active HIGH)
Description
0
–P
3
) is loaded
2
the design of multistage counters, as indicated in Figure
1 and Figure 2. In Figure 1, each RC output is used as
the clock input for the next higher stage. This configura-
tion is particularly advantageous when the clock source
has a limited drive capability, since it drives only the first
stage. To prevent counting in all stages it is only neces-
sary to inhibit the first stage, since a HIGH signal on CE
inhibits the RC output pulse, as indicated in the RC Truth
Table. A disadvantage of this configuration, in some
applications, is the timing skew between state changes
in the first and last stages. This represents the cumula-
tive delay of the clock as it ripples through the preceding
stages.
A method of causing state changes to occur simulta-
neously in all stages is shown in Figure 2. All clock
inputs are driven in parallel and the RC outputs propa-
gate the carry/borrow signals in ripple fashion. In this
configuration the LOW state duration of the clock must
be long enough to allow the negative-going edge of the
carry/borrow signal to ripple through to the last stage
before the clock goes HIGH. There is no such restriction
on the HIGH state duration of the clock, since the RC
output of any device goes HIGH shortly after its CP input
goes HIGH.
The configuration shown in Figure 3 avoids ripple delays
and their associated restrictions. The CE input for a
given stage is formed by combining the TC signals from
all the preceding stages. Note that in order to inhibit
counting an enable signal must be included in each carry
gate. The simple inhibit scheme of Figure 1 and Figure 2
doesn’t apply, because the TC output of a given stage is
not affected by its own CE.
HIGH / LOW
50 / 33.3
50 / 33.3
50 / 33.3
1.0 / 3.0
1.0 / 1.0
1.0 / 1.0
1.0 / 1.0
1.0 / 1.0
U.L.
Output I
20µA / -0.6 mA
20µA / -0.6 mA
20µA / -1.8mA
20µA / -0.6mA
20µA / -0.6mA
Input I
-1mA / 20mA
-1mA / 20mA
-1mA / 20mA
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/ I
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