MC33899 Freescale Semiconductor, MC33899 Datasheet - Page 15

• Manufacturer Part Number: MC33899
• Description: Programmable H-Bridge Power IC
• Manufacturer: Freescale Semiconductor

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LOW-SIDE CURRENT COMPARATOR VS.
CURRENT LIMIT LEVELS
side MOSFETs: current comparator and current limit. Current
comparator is the normal commanded switching current.
Current limit is for fault protection.
comparator tripping. Once the low-side current comparator
has tripped and filter time expired, the low-side MOSFET
turns off and the high-side MOSFET subsequently turns on
for normal current re-circulation in the load. If an actual hard
short to either VIGNP or ground on the S0/S1 outputs is
encountered, the current limit kicks in and prevents large
current spikes from VIGNP (or to ground) to occur. The
threshold level of the current comparator vs. the high- and
low-side current limits is given in the Static Electrical
Characteristics table, page 8.
controller to limit current spike during timer operations.
SERIAL PERIPHERAL INTERFACE (SPI)
Chip Select (
and Serial Data In (DI). This device is configured as a SPI
slave and is daisy-chainable (single
slaves).
CHIP SELECT (CS)
serial transfers. On the falling edge of
released from tri-state mode, and all status information is
latched in the SPI shift register. While
data is shifted into the DI pin and shifted out of the DO pin on
each subsequent SCLK. On the rising edge of
Analog Integrated Circuit Device Data
Freescale Semiconductor
There are two different current limit thresholds for the low-
The inductance of the load results in just the current
As backup protection, there is a linear overcurrent
The 33899 has a serial peripheral interface consisting of
The
CS
is a low = true input that selects this device for
CS
), Serial Clock (SCLK), Serial Data Out (DO),
REDIS
PWM
Figure 9. Re-enable after a Low Side Current Comparator Trip
t = 33.3 * C (nF) µs
t
min
= 25 µs
CS
CS
CS
LS Current Comparator
for multiple SPI
is asserted, register
, the DO pin is
CS
, the DO pin
4 VDC
Reset to
0 VDC
is placed in a high impedance state and the Fault register
reloaded (latched) with the current filtered status data. To
allow sufficient time to reload the Fault register, the
must remain low for a minimum of t
again.
50 ns or shorter. (DO may come out of tri-state, but no status
bits are cleared and no control bits are changed.)
pulls this pin to V
pin has TTL-level compatible input voltages, which allows
proper operation with microprocessors using a 3.0 V to 5.0 V
supply.
SERIAL CLOCK (SCLK)
synchronization of serial data transfer. This pin has TTL-level
compatible input voltages, which allow proper operation with
microprocessors using a 3.3 V to 5.0 V supply.
33899 latch input data on the rising edge of SCLK. The SPI
master typically shifts data out on the falling edge of SCLK,
while the 33899 shifts data out on the falling edge of SCLK to
allow more time to drive the DO pin to the proper level.
SERIAL DATA OUTPUT (DO)
the MSB is the first bit of the word transmitted on DO and the
LSB is the last bit of the word transmitted on DO. After all 8
bits of the fault register are transmitted, the DO output
sequentially transmits the digital data that was just received
on the DI pin. This allows the processor to distinguish a
shorted DI pin condition. The DO output continues to transmit
By design, the
The
The SCLK input is the clock signal input for
When
The DO is the SPI data out pin. When
CS
CS
input has a 50 µA current source to VCC, which
is asserted, both the microprocessor and the
t = 33.3 * C (nF) µs
t
CC
min
CS
if an open circuit condition occurs. This
= 25 µs
input is immune to spurious pulses of
I
load
FUNCTIONAL PIN DESCRIPTION
FUNCTIONAL DESCRIPTION
CSN
Reset to
0 VDC
prior to going high
CS
is asserted (low),
CS
pin
33899
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