MC740-430E ETC, MC740-430E Datasheet

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MC740-430E

Manufacturer Part Number
MC740-430E
Description
47-Gb/s 4:1 Multiplexer
Manufacturer
ETC
Datasheet
NEL
FEATURES
APPLICATIONS
FUNCTION DIAGRAM
The MC740-430E is an engineering sample of 47-Gb/s signal generator. It consists of a 4:1
multiplexer (MUX), D-type flipflop (D-FF), and clock distribution unit based on 0.1-µm InP-HEMT
devices. Four-parallel data inputs are multiplexed to 47-Gb/s data by using 47- and 11.75-GHz
clock signals. At the output stage, the D-FF regenerates the muliplexed data with the 47-GHz clock
signal and offers symmetrical eye openings. The MC740-430E has SCFL (Source Coupled FET
Logic) I/O and can be directly connected to a pulse pattern generator.
Operating range:
Signal regeneration with full-rate clock signal
Large output amplitude:
Single power supply voltage:
(note) 50-Gb/s operation is optional.
Parallel-to-serial converters, Test equipments
DATA 3, 2, 1, 0
CLK10
CLK10
4
47-Gb/s 4:1 Multiplexer
Latching stage
2
50 Ω
50 Ω
Fig. 1. Function diagram.
MC740-430E
65 Ω
SCFL I/O (V
DC -6 V
38 to 47 Gb/s (min.)
Clock Distributor
20Gb/s
(mon.)
4:1 MUX
- 1 -
2
75 Ω
OHD
40Gb/s
(mon.)
10-dB
= 0V, V
ATT
(note)
OLD
D-FF
75 Ω
75 Ω
= -0.9V, typ.)
50 Ω
50 Ω
MD-01-4-43-75-482
DATA
DATA
φshifter
CLK40
CLK40
May 8, 2002
Preliminary

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MC740-430E Summary of contents

Page 1

... NEL 47-Gb/s 4:1 Multiplexer The MC740-430E is an engineering sample of 47-Gb/s signal generator. It consists of a 4:1 multiplexer (MUX), D-type flipflop (D-FF), and clock distribution unit based on 0.1-µm InP-HEMT devices. Four-parallel data inputs are multiplexed to 47-Gb/s data by using 47- and 11.75-GHz clock signals. At the output stage, the D-FF regenerates the muliplexed data with the 47-GHz clock signal and offers symmetrical eye openings ...

Page 2

... Fig. 2. Timing charts MC740-430E ...

Page 3

... Odd 14 16 Fig. 3. Front and rear panels. Case dimension (without connectors) height width: 370 mm depth: 235 MC740-430E FUNCTION 20G Monitor Even (Even ch., DATA2 and 0) 20G Monitor Odd (Odd ch., DATA3 and 1) 1/4 Clock Output 40G Monitor (4:1 MUX Output) PWR Power Supply (-6.0 V) GND Ground (0 ...

Page 4

... Monitor Output Interface 40Gb/s 20Gb/s 20-Gb/s Monitor Output Interface ( odd, even) 10-GHz Clock Output Interface CLK10 PARAMETER Storage Temperature PARAMETER PARAMETER PARAMETER - 4 - MC740-430E Ratings TBD TBD Ratings -1 -1.6 to +1.6 V (DC), 1.6 Vpp (AC) -1.6 to +1.6 V (DC), 1.6 Vpp (AC) Ratings TBD -1.2 to 1.2 V (DC Input -1.75 to +0.2 V Conditions TBD -1 ...

Page 5

... Operating Temperature Ta (note1) NEL recommends a DC power supply with an output current capacity and an output voltage ripple less than 10 mV rms. (note2) The MC740-430E should be protected from condensation. DATA and CLOCK INPUT SIGNALS SYMBOL DATA3 to 0 40-GHz Clock Input Interface CLK40 ...

Page 6

... Output Voltage Amplitude of CLK40 O40 C Output Voltage Amplitude of CLK10 O10 V Output Voltage, High (CLK10) OHC10 V Output Voltage, Low (CLK10) OLC10 PARAMETER Power Supply Current Power Dissipation PARAMETER Maximum Skew PARAMETER - 6 - MC740-430E MIN. TYP. MAX. -0.2 0.0 -0.9 -0.8 TBD 0.0 -0.9 TBD 7.0 TBD 42 TBD MIN. TYP. MAX. ...

Page 7

... Output Voltage Amplitude of 4:1 MUX V ampM40 (with an internal 10-dB attenuator) Output Voltage Amplitude of 20 Gb/s Data, V ampM20 C Output Voltage Amplitude of CLK10 M10 V Output Voltage, High (CLK10) OHM10 V Output Voltage, Low (CLK10) OLM10 PARAMETER (Odd, Even MC740-430E MIN. TYP. MAX. - 0.3 - 0.9 0.5 0.7 (TBD) TBD -0.2 -0.9 TBD UNITS Vpp Vpp Vpp ...

Page 8

... DATA3 to 1 CLK10 (2) Data and Clock Output Signals . DATA, DATA CLK40 CLK10 (3) Monitor Output Signals 40Gb/s 20Gb/s odd, even CLK10 50% Skew 80% 80% 20% 20 Fig. 4. Definitions of symbols MC740-430E C I40 V center I10 center 50 ampD OHD V OLD C O40 V OHC10 ...

Page 9

... DATA2 DATA1 DATA0 CLK10 CLK40 1 V/div, 20 ps/div DATA DATA CLK40 300 mV/div, 5 ps/div Measurement conditions Ta = 25℃, VPWR = -6 DATA3 to 0: 11.75-Gb/s (2 -1) pseudo-random binary sequence Sampling Oscilloscope: Agilent digital communication analyzer (86100A) and plug-in module (83484A) Cable: SUHNER SUCOFLEX102 (30 cm MC740-430E ...

Page 10

... Step 3 Step 4 Delay adjustment To operate the MC740-430E normally, the following delay adjustments are needed (refer to the function diagram, Fig. 1, and sample implementation, Fig. 9). (1) CLK10 output: Adjust the timing between the input data (after latching) and the internal clock at the 4:1 MUX. ...

Page 11

... Fig. 6. 20G and 40G monitor output waveforms. DATA Latching stage CLK10 input Fig. 7. Delay adjustment by CLK10 input MC740-430E . pp 20 psV/div 20 psV/div latched data 4 4:1 MUX internal clock When the 20G ...

Page 12

... Turn-off sequence is shown in Table. 2. Turn-off sequence Step 1 Step 2 Step 3 Step 4 (a) with an unsuitable delay (b) after delay adjustment at ”φshifter” Fig. 8. DFF output waveforms. Table 2 Turn-off sequence Procedure RF inputs off. Front switch off. Main switch (rear panel) off off MC740-430E 10 ps/div 10 ps/div ...

Page 13

... MC740-430E 50 Ω 8 CLK40 (input) 50 Ω DATA3 Ω CLK10 (input) 65 Ω CLK10 (output PWR Fig. 9. Sample implementation MC740-430E 70 Ω DATA, DATA Ω Ω CLK40 Ω (output) 65 Ω 15 CLK10 (monitor Ω 70 Ω 16 10-dB 50 Ω 40Gb/s ATT (mon ...

Page 14

... Confirm that the voltages of all surrounding materials including human body which touch the 3. modules are less than 0.2 V. Please measure these voltages using an oscilloscope (Do not use DC and AC voltmeters). 4. Make sure that there is no abnormal spike on the power supply voltage. 5. Ground all soldering iron tips. Leak voltage should be less than 0 MC740-430E ...

Page 15

... NTT Electronics Corp. shall not assume any liability for damage that may result from the use of these circuit drawings etc. NTT Electronics Corp. shall not assent to or guarantee any rights of execution for patent rights of the third parties and other rights that may be raised for use of these circuit drawings ...

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