CY7C4245V-15ASXC Cypress Semiconductor Corp, CY7C4245V-15ASXC Datasheet - Page 5

• Manufacturer Part Number: CY7C4245V-15ASXC
• Description: IC SYNC FIFO MEM 4KX18 64LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr

Specifications of CY7C4245V-15ASXC

• Access Time: 10ns
• Memory Size: 72K (4K x 18)
• Package / Case: 64-LQFP
• Function: Synchronous
• Data Rate: 67MHz
• Voltage - Supply: 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Number Of Circuits: 2
• Data Bus Width: 18 bit
• Bus Direction: Unidirectional
• Timing Type: Synchronous
• Organization: 4 K x 18
• Maximum Clock Frequency: 66.7 MHz
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Current: 30 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-1716

Document #: 38-06029 Rev. *C
Flag Operation
The CY7C42X5V devices provide five flag pins to indicate the
condition of the FIFO contents. Empty and Full are
synchronous. PAE and PAF are synchronous if V
is tied to V
Full Flag
The Full Flag (FF) will go LOW when device is Full. Write
operations are inhibited whenever FF is LOW regardless of the
state of WEN. FF is synchronized to WCLK, i.e., it is exclu-
sively updated by each rising edge of WCLK.
Empty Flag
The Empty Flag (EF) will go LOW when the device is empty.
Read operations are inhibited whenever EF is LOW,
regardless of the state of REN. EF is synchronized to RCLK,
i.e., it is exclusively updated by each rising edge of RCLK.
Programmable Almost Empty/Almost Full Flag
The CY7C42X5V features programmable Almost Empty and
Almost Full Flags. Each flag can be programmed (described
in the Programming section) a specific distance from the corre-
sponding boundary flags (Empty or Full). When the FIFO
contains the number of words or fewer for which the flags have
been programmed, the PAF or PAE will be asserted, signifying
Table 2. Flag Truth Table
0
1 to n
(n + 1) to 32
33 to (64 − (m + 1))
(64 − m)
64
0
1 to n
(n + 1) to 512
513 to (1024 − (m + 1))
(1024 − m)
1024
Note:
2. n = Empty Offset (Default Values: CY7C4425V n = 7, CY7C4205V n = 31, CY7C4215V n = 63, CY7C4225V/7C4235V/7C4245V n = 127).
3. m = Full Offset (Default Values: CY7C4425V n = 7, CY7C4205V n = 31, CY7C4215V n = 63, CY7C4225V/7C4235V/7C4245V n = 127).
7C4425V - 64 x 18
7C4225V - 1K x 18
[2]
[2]
[3]
SS
to 63
[3]
.
to 1023
Number of Words in FIFO
Number of Words in FIFO
0
1 to n
(n + 1) to 128
129 to (256 − (m + 1))
(256 − m)
256
0
1 to n
(n + 1) to 1024
1025 to (2048 − (m + 1))
(2048 − m)
2048
7C4205V - 256 x 18
7C4235V - 2K x 18
[2]
[2]
[3]
[3]
to 255
to 2047
CC
/SMODE
0
1 to n
(n + 1) to 256
257 to (512 − (m + 1))
(512 − m)
512
0
1 to n
(n + 1) to 2048
2049 to (4096 − (m + 1))
(4096 − m)
4096
7C4215V - 512 x 18
7C4245V - 4K x 18
[2]
[2]
[3]
that the FIFO is either Almost Full or Almost Empty. See
Table 2 for a description of programmable flags.
When the SMODE pin is tied LOW, the PAF flag signal
transition is caused by the rising edge of the write clock and
the PAE flag transition is caused by the rising edge of the read
clock.
Retransmit
The retransmit feature is beneficial when transferring packets
of data. It enables the receipt of data to be acknowledged by
the receiver and retransmitted if necessary.
The Retransmit (RT) input is active in the standalone and width
expansion modes. The retransmit feature is intended for use
when a number of writes equal to or less than the depth of the
FIFO have occurred since the last RS cycle. A HIGH pulse on
RT resets the internal read pointer to the first physical location
of the FIFO. WCLK and RCLK may be free running but must
be disabled during and tRTR after the retransmit pulse. With
every valid read cycle after retransmit, previously accessed
data is read and the read pointer is incremented until it is equal
to the write pointer. Flags are governed by the relative
locations of the read and write pointers and are updated during
a retransmit cycle. Data written to the FIFO after activation of
RT are transmitted also.
The full depth of the FIFO can be repeatedly retransmitted.
[3]
to 511
to 4095
CY7C4225V/4205V/4215V
CY7C4425V/4235V/4245V
FF
FF
H
H
H
H
H
H
H
H
H
H
L
L
PAF
PAF
H
H
H
H
H
H
H
H
L
L
L
L
HF
HF
H
H
H
H
H
H
L
L
L
L
L
L
PAE
PAE
H
H
H
H
H
H
H
H
L
L
L
L
Page 5 of 20
EF
EF
H
H
H
H
H
H
H
H
H
H
L
L
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