IDT72V271LA10PFG IDT, Integrated Device Technology Inc, IDT72V271LA10PFG Datasheet - Page 20

• Manufacturer Part Number: IDT72V271LA10PFG
• Description: IC FIFO SYNC 3.3V 10NS 64-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V271LA10PFG

• Function: Synchronous
• Memory Size: 288K (16K x 18)
• Access Time: 10ns
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Configuration: Dual
• Density: 288Kb
• Access Time (max): 6.5ns
• Word Size: 9b
• Organization: 32Kx9
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: TQFP
• Clock Freq (max): 100MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 55mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Rate: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 72V271LA10PFG; 800-1523

NOTES:
1. Retransmit setup is complete after EF returns HIGH, only then can a read operation begin.
2. OE = LOW.
3. W
4. No more than D –2 may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be HIGH throughout the Retransmit setup procedure.
5. EF goes HIGH at 60 ns + 1 RCLK cycle + t
IDT72V261LA/72V271LA
3.3 VOLT CMOS SuperSync FIFO™ 16,384 x 9 and 32,768 x 9
D = 16,384 for IDT72V261LA and 32,768 for IDT72V271LA.
Q
1
WCLK
RCLK
0
= first word written to the FIFO after Master Reset, W
WEN
REN
PAE
PAF
- Q
HF
EF
RT
n
t
ENS
W
x
t
t
A
ENH
t
ENS
t
RTS
REF
t
.
RTS
Figure 11. Retransmit Timing (IDT Standard Mode)
2
= second word written to the FIFO after Master Reset.
t
t
t
ENH
REF
HF
t
SKEW4
1
W
x+1
2
20
t
PAF
1
t
ENS
2
t
t
t
A
REF
PAE
COMMERCIAL AND INDUSTRIAL
(5)
W
TEMPERATURE RANGES
1
(3)
JANUARY 30, 2009
t
t
A
ENH
4673 drw14
W
2
(3)