IDT72V36100L15PFI IDT, Integrated Device Technology Inc, IDT72V36100L15PFI Datasheet - Page 36

• Manufacturer Part Number: IDT72V36100L15PFI
• Description: IC FIFO SYNC II 36BIT 128-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V36100L15PFI

• Function: Synchronous
• Memory Size: 2.3K (64 x 36)
• Data Rate: 166MHz
• Access Time: 15ns
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Configuration: Dual
• Density: 2.25Mb
• Access Time (max): 10ns
• Word Size: 36b
• Organization: 64Kx36
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: TQFP
• Clock Freq (max): 66.7MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.15V
• Operating Supply Voltage (max): 3.45V
• Supply Current: 40mA
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V36100L15PFI; 800-1529

NOTES:
1. m = PAF offset.
2. D = maximum FIFO Depth.
3. PAF is asserted to LOW on WCLK transition and reset to HIGH on RCLK transition.
4. Select this mode by setting PFM LOW during Master Reset.
WCLK
NOTES:
1. n = PAE offset.
2. For IDT Standard mode
3. For FWFT mode.
4. t
5. PAE is asserted and updated on the rising edge of WCLK only.
6. Select this mode by setting PFM HIGH during Master Reset.
WCLK
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II
65,536 x 36 and 131,072 x 36
RCLK
RCLK
WEN
REN
WEN
In IDT Standard Mode: D = 65,536 for the IDT72V36100 and 131,072 for the IDT72V36110.
In FWFT Mode: D = 65,537 for the IDT72V36100 and 131,073 for the IDT72V36110.
WCLK and the rising edge of RCLK is less than t
REN
PAE
PAF
SKEW2
t
CLKH
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH (after one RCLK cycle plus t
Figure 19. Synchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
Figure 20. Asynchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
t
ENS
n words in FIFO
n+1 words in FIFO
t
CLKL
D - (m + 1) words in FIFO
t
ENH
(2)
t
SKEW2
1
,
(3)
t
CLKH
SKEW2
(4)
, then the PAE deassertion may be delayed one extra RCLK cycle.
t
PAES
2
t
ENS
TM
36-BIT FIFO
t
CLKL
36
t
ENS
t
t
ENH
PAFA
n+1 words in FIFO
n+2 words in FIFO
t
ENS
t
ENH
D - m words
in FIFO
(2)
(3)
,
t
PAFA
1
COMMERCIAL AND INDUSTRIAL
PAES
t
PAES
). If the time between the rising edge of
D - (m + 1) words
TEMPERATURE RANGES
2
OCTOBER 22, 2008
in FIFO
n words in FIFO
n+1 words in FIFO
6117 drw25
6117 drw 24
(2)
,
(3)