IDT72V36100L15PFI IDT, Integrated Device Technology Inc, IDT72V36100L15PFI Datasheet - Page 46

• Manufacturer Part Number: IDT72V36100L15PFI
• Description: IC FIFO SYNC II 36BIT 128-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V36100L15PFI

• Function: Synchronous
• Memory Size: 2.3K (64 x 36)
• Data Rate: 166MHz
• Access Time: 15ns
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Configuration: Dual
• Density: 2.25Mb
• Access Time (max): 10ns
• Word Size: 36b
• Organization: 64Kx36
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: TQFP
• Clock Freq (max): 66.7MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3.15V
• Operating Supply Voltage (max): 3.45V
• Supply Current: 40mA
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 128
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V36100L15PFI; 800-1529

THE INSTRUCTION REGISTER
processor at the rising edge of TCLK.
register to be accessed, or both. The instruction shifted into the register is latched
at the completion of the shifting process when the TAP controller is at Update-
IR state.
which can hold instruction data. These mandatory cells are located nearest the
serial outputs they are the least significant bits.
TEST DATA REGISTER
Boundary Scan register and Device ID register.
and a common serial data output.
complete description, refer to the IEEE Standard Test Access Port Specification
(IEEE Std. 1149.1-1990).
TEST BYPASS REGISTER
to TDO. It contains a single stage shift register for a minimum length in serial path.
When the bypass register is selected by an instruction, the shift register stage
is set to a logic zero on the rising edge of TCLK when the TAP controller is in
the Capture-DR state.
operation of the device in response to the BYPASS instruction.
THE BOUNDARY-SCAN REGISTER
out of the processor input/output ports. The Boundary Scan Register is a part
of the IEEE 1149.1-1990 Standard JTAG Implementation.
THE DEVICE IDENTIFICATION REGISTER
specify the manufacturer, part number and version of the processor to be
determined through the TAP in response to the IDCODE instruction.
is dropped in the 11-bit Manufacturer ID field.
following values:
IDT72V36100/72V36110 3.3V HIGH DENSITY SUPERSYNC II
65,536 x 36 and 131,072 x 36
31(MSB)
Version (4 bits)
0X0
The Instruction register allows an instruction to be shifted in serially into the
The Instruction is used to select the test to be performed, or the test data
The instruction register must contain 4 bit instruction register-based cells
The Test Data register contains three test data registers: the Bypass, the
These registers are connected in parallel between a common serial input
The following sections provide a brief description of each element. For a
The register is used to allow test data to flow through the device from TDI
The operation of the bypass register should not have any effect on the
The Boundary Scan Register allows serial data TDI be loaded in to or read
The Device Identification Register is a Read Only 32-bit register used to
IDT JEDEC ID number is 0xB3. This translates to 0x33 when the parity
For the IDT72V36100/72V36110, the Part Number field contains the
IDT72V36100/72V36110 JTAG Device Identification Register
28 27
Part Number (16-bit) Manufacturer ID (11-bit)
IDT72V36100
IDT72V36110
Device
12 11
Part# Field
0X33
04DE
04DF
TM
1 0(LSB)
36-BIT FIFO
1
46
JTAG INSTRUCTION REGISTER
when the TAP controller is in the Shift-IR state. The instruction is decoded to
perform the following:
different possible instructions. Instructions are decoded as follows.
a complete description refer to the IEEE Standard Test Access Port Specification
(IEEE Std. 1149.1-1990).
EXTEST
test mode and selects the boundary-scan register to be connected between TDI
and TDO. During this instruction, the boundary-scan register is accessed to
drive test data off-chip via the boundary outputs and receive test data off-chip
via the boundary inputs. As such, the EXTEST instruction is the workhorse of
IEEE. Std 1149.1, providing for probe-less testing of solder-joint opens/shorts
and of logic cluster function.
IDCODE
and selects the optional device identification register to be connected between
TDI and TDO. The device identification register is a 32-bit shift register containing
information regarding the IC manufacturer, device type, and version code.
Accessing the device identification register does not interfere with the operation
of the IC. Also, access to the device identification register should be immediately
available, via a TAP data-scan operation, after power-up of the IC or after the
TAP has been reset using the optional TRST pin or by otherwise moving to the
Test-Logic-Reset state.
SAMPLE/PRELOAD
normal functional mode and selects the boundary-scan register to be connected
between TDI and TDO. During this instruction, the boundary-scan register can
be accessed via a date scan operation, to take a sample of the functional data
entering and leaving the IC. This instruction is also used to preload test data into
the boundary-scan register before loading an EXTEST instruction.
Hex
Value
0x00
0x02
0x01
0x03
0x0F
The required EXTEST instruction places the IC into an external boundary-
The optional IDCODE instruction allows the IC to remain in its functional mode
The required SAMPLE/PRELOAD instruction allows the IC to remain in a
The Instruction register allows instruction to be serially input into the device
•
•
The Instruction Register is a 4 bit field (i.e.IR3, IR2, IR1, IR0) to decode 16
The following sections provide a brief description of each instruction. For
Select test data registers that may operate while the instruction is
current. The other test data registers should not interfere with chip
operation and the selected data register.
Define the serial test data register path that is used to shift data between
TDI and TDO during data register scanning.
Instruction
EXTEST
IDCODE
SAMPLE/PRELOAD
HIGH-IMPEDANCE
BYPASS
Table 6. JTAG Instruction Register Decoding
Select Chip Identification data register
Function
Select Boundary Scan Register
Select Boundary Scan Register
JTAG
Select Bypass Register
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
OCTOBER 22, 2008