IDT72401L10P IDT, Integrated Device Technology Inc, IDT72401L10P Datasheet - Page 4

• Manufacturer Part Number: IDT72401L10P
• Description: IC FIFO PAR 64X4 10NS 16-DIP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 7200r

Specifications of IDT72401L10P

• Function: Asynchronous
• Memory Size: 256 (64 x 4)
• Data Rate: 10MHz
• Access Time: 10ns
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 16-DIP (0.300", 7.62mm)
• Configuration: Dual
• Density: 256b
• Word Size: 4b
• Organization: 64x4
• Sync/async: Asynchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: PDIP
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Supply Current: 35mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 16
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72401L10P

AC TEST CONDITIONS
CAPACITANCE
(T
NOTE
1. Characterized values, not currently tested.
SIGNAL DESCRIPTIONS
INPUTS:
DATA INPUT (D
CONTROLS:
SHIFT IN (SI)
can be written to the FIFO via the D
SHIFT OUT (SO)
be read from the FIFO via the Data Output (Q
MASTER RESET (MR)
FIFO should be cleared with a MR. MR is active LOW.
IDT72401/72403
CMOS PARALLEL FIFO 64 x 4, 64 x 5
A
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
Symbol
C
C
Data input lines. The IDT72401 and IDT72403 have a 4-bit data input.
Shift In controls the input of the data into the FIFO. When SI is HIGH, data
Shift Out controls the output of data of the FIFO. When SO is HIGH, data can
Master Reset clears the FIFO of any data stored within. Upon power up, the
= +25°C, f = 1.0MHz)
IN
OUT
:
Input Capacitance
Output Capacitance
0
-
3
Parameter
)
0
-
3
lines.
V
V
Conditions
IN
OUT
= 0V
0
-
= 0V
3
) lines.
GND to 3.0V
See Figure 1
1.5V
1.5V
3ns
Max.
5
7
Unit
pF
pF
4
INPUT READY (IR)
to it. When IR is LOW the FIFO is unavailable for new input data. IR is also used
to cascade many FlFOs together, as shown in Figures 10 and 11.
OUTPUT READY (OR)
OR is LOW, the FIFO is unavailable for new output data. OR is also used to
cascade many FlFOs together, as shown in Figures 10 and 11.
OUTPUT ENABLE (OE) (IDT72403 ONLY)
OUTPUTS:
DATA OUTPUT (Q
ALL INPUT PULSES:
When Input Ready is HIGH, the FIFO is ready for new input data to be written
When Output Ready is HIGH, the output (Q
Output enable is used to read FIFO data onto a bus. OE is active LOW.
Data Output lines. The IDT72401 and IDT72403 have a 4-bit data output.
GND
3.0V
0
560Ω
-
<3ns
3
)
10%
Figure 1. AC Test Load
90%
*Including scope and jig
5V
or equivalent circuit
1.1KΩ
30pF*
MILITARY AND COMMERCIAL
OUTPUT
TEMPERATURE RANGES
0
-
3
) contains valid data. When
2747 drw 05
90%
10%
<3ns
2747 drw 04