IDT72401L10P IDT, Integrated Device Technology Inc, IDT72401L10P Datasheet - Page 8

• Manufacturer Part Number: IDT72401L10P
• Description: IC FIFO PAR 64X4 10NS 16-DIP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 7200r

Specifications of IDT72401L10P

• Function: Asynchronous
• Memory Size: 256 (64 x 4)
• Data Rate: 10MHz
• Access Time: 10ns
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 16-DIP (0.300", 7.62mm)
• Configuration: Dual
• Density: 256b
• Word Size: 4b
• Organization: 64x4
• Sync/async: Asynchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: PDIP
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Supply Current: 35mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 16
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72401L10P

NOTES:
1. When the memory is empty, the last word will remain on the outputs until the MR is strobed or a new data word falls through to the output. However, OR will remain LOW,
2. When the output data changes as a result of a pulse on SO, the OR signal always goes LOW before there is any change in output data and stays LOW until the new data
3. If SO is held HIGH while the memory is empty and a word is written into the input, that word will appear at the output after a fall-through time. OR will go HIGH for one
4. When the MR is brought LOW, the outputs are cleared to LOW, IR goes HIGH and OR goes LOW. If SI is HIGH when the MR goes HIGH, the data on the inputs will be
5. FIFOs are expandable on depth and width. However, in forming wider words, two external gates are required to generate composite Input and OR flags. This is due to the
IDT72401/72403
CMOS PARALLEL FIFO 64 x 4, 64 x 5
indicating data at the output is not valid.
has appeared on the outputs. Anytime OR is HIGH, there is valid stable data on the outputs.
internal cycle (at least t
first word and will not appear on the outputs until SO has been brought LOW.
written into the memory and IR will return to the LOW state until SI is brought LOW. If SI is LOW when the MR is ended, IR will go HIGH, but the data in the inputs will not
enter the memory until SI goes HIGH.
variation of delays of the FIFOs.
COMPOSITE
SHIFT IN
READY
INPUT
ORL
) and then go back LOW again. The stored word will remain on the outputs. If more words are written into the FIFO, they will line up behind the
D
D
D
D
D
D
D
D
D
D
D
D
IR
IR
IR
SI
SI
SI
0
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0
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3
MR
MR
MR
Figure 11. 192 x 12 Depth and Width Expansion
OR
OR
OR
SO
SO
SO
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Q
0
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IR
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SI
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MR
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8
OR
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SO
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IR
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IR
SI
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MR
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OR
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SO
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SO
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MILITARY AND COMMERCIAL
TEMPERATURE RANGES
SHIFT OUT
COMPOSITE
OUTPUT
READY
MR
2747 drw 15