HT45RM03 Holtek Semiconductor, HT45RM03 Datasheet - Page 11

• Manufacturer Part Number: HT45RM03
• Description: Brushless DC Motor Type 8-Bit OTP MCU
• Manufacturer: Holtek Semiconductor

During the execution of an interrupt subroutine, other in-
terrupt acknowledgments are held until the RETI in-
struction is executed or the EMI bit and the related
interrupt control bit are set to 1 (of course, if the stack is
not full). To return from the interrupt subroutine, RET or
able an interrupt service, but RET will not.
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding inter-
rupts are enabled. In the case of simultaneous requests
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
The Comparator interrupt request flag (CF), external in-
terrupt 1 request flag (EI1F), External Interrupt 0 request
flag (EI0F), Enable Comparator 0 output interrupt bit
(EC0I), Enable External interrupt 1 bit (EEI1), Enable
External Interrupt 0 bit (EEI0), and enable master inter-
rupt bit (EMI) make up of the Interrupt Control register 0
(INTC0) which is located at 0BH in the RAM.
The PWM period interrupt request flag (PWMF), the
Timer/Event Counter 1 interrupt request flag (T1F), the
Timer/Event Counter 0 interrupt request flag (T0F), en-
able PWM period interrupt bit (EPWMI), enable
Timer/Event Counter 1 interrupt bit (ET1I), and enable
Timer/Event Counter 0 interrupt bit (ET0I), constitute the
Interrupt Control register 1 (INTC1) which is located at
1EH in the RAM.
EMI, EEI0, EEI1, ECI, ET0I, ET1I, and EPWMI are all
used to control the enable/disable status of interrupts.
These bits prevent the requested interrupt from being
Rev. 1.00
RETI may be invoked. RETI will set the EMI bit to en-
Comparator output Interrupt
External INT0A, INT0B, INT0C
Interrupt
External INT1 Interrupt
PWM Period Interrupt
Timer/Event Counter 0 Overflow
Timer/Event Counter 1 Overflow
Bit No.
3, 7
0
1
2
4
5
6
Interrupt Source
EPWMI Control the PWM period interrupt (1=enabled; 0=disabled)
PWMF
Label
ET0I
ET1I
T0F
T1F
Control the Timer/Event Counter 0 interrupt (1=enabled; 0=disabled)
Control the Timer/Event Counter 1 interrupt (1=enabled; 0=disabled)
Unused bit, read as 0 .
PWM period request flag (1=active; 0=inactive)
Internal Timer/Event Counter 0 request flag (1=active; 0=inactive)
Internal Timer/Event Counter 1 request flag (1=active; 0=inactive)
Priority
1
2
3
4
5
6
Vector
INTC1 (1EH) Register
0CH
04H
08H
10H
14H
18H
11
serviced. Once the interrupt request flags (EI0F, EI1F,
CF, T0F, T1F, PWMF) are all set, they remain in the
INTC1 or INTC0 respectively until the interrupts are ser-
viced or cleared by a software instruction.
It is recommended that a program does not use the
rupts often occur in an unpredictable manner or need to
be serviced immediately in some applications. If only one
stack is left and enabling the interrupt is not well con-
trolled, the original control sequence will be damaged
once the CALL operates in the interrupt subroutine.
Oscillator Configuration
There are two oscillator circuits in the microcontroller.
Both are designed for system clocks, namely the RC os-
cillator and the Crystal oscillator, which are determined
by options. No matter what oscillator type is selected,
the signal provides the system clock. The HALT mode
stops the system oscillator and ignores an external sig-
nal to conserve power.
If an RC oscillator is used, an external resistor between
OSC1 and VSS is required and the resistance must
range from 24k to 1M . The system clock, divided by 4,
is available on OSC2 with pull-high resistor, which can be
used to synchronize external logic. The RC oscillator pro-
vides the most cost effective solution. However, the fre-
quency of oscillation may vary with VDD, temperatures
and the chip itself due to process variations. It is, there-
fore, not suitable for timing sensitive operations where an
accurate oscillator frequency is desired.
If the Crystal oscillator is used, a crystal across OSC1
and OSC2 is needed to provide the feedback and phase
shift required for the oscillator, and no other external
components are required. Instead of a crystal, a resona-
CALL subroutine within the interrupt subroutine. Inter-
Function
System Oscillator
HT45RM03
January 11, 2007