HT46801N-1 Holtek Semiconductor, HT46801N-1 Datasheet
HT46801N-1
Related parts for HT46801N-1
HT46801N-1 Summary of contents
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Technical Document Application Note HA0075E MCU Reset and Oscillator Circuits Application Note Features CPU Features Operating voltage 4MHz: 2.2V~5.5V SYS f = 8MHz: 3.3V~5.5V SYS f = 12MHz: 4.5V~5.5V SYS Up to 0.33 s instruction cycle with ...
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Selection Table Program Part No. Memory HT46R01B HT46R01N HT48R01B HT48R01N Block Diagram The following block diagram illustrates the main functional blocks. Pin Assignment Rev.1.00 Data 8-bit Time HIRC RTC I/O Memory ...
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Pin Description The function of each pin is listed in the following tables, however the details behind how each pin is configured is con- tained in the other individual peripheral function sections. HT46R01B-1 Pin Name Function PA0/AN0 PA1/PFD/AN1 PA2/TC0/AN2 ...
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HT46R01N-1 Pin Name Function PA0/AN0 PA1/PFD/AN1 PA2/TC0/AN2 PA3/INT/AN3 PA4/TC1/PWM PA5/OSC2 OSC2 PA6/OSC1 OSC1 PA7/RES PB0 PB1 VDD VSS Note: OPT: Optional by configuration option (CO) or register option I/T: Input type O/T: Output type CO: Configuration option ST: Schmitt ...
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HT48R01B-1 Pin Name Function PA0 PA0 PA1 PA1/PFD PFD PA2 PA2/TC0 TC0 PA3 PA3/INT INT PA4 PA4/TC1 TC1 PA5 PA5/OSC2 OSC2 PA6 PA6/OSC1 OSC1 PA7 PA7/RES RES VDD VDD VSS VSS Note: OPT: Optional by configuration option (CO) or ...
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HT48R01N-1 Pin Name Function PA0 PA0 PA1 PA1/PFD PFD PA2 PA2/TC0 TC0 PA3 PA3/INT INT PA4 PA4/TC1 TC1 PA5 PA5/OSC2 OSC2 PA6 PA6/OSC1 OSC1 PA7 PA7/RES RES PB0 PB0 PB1 PB1 VDD VDD VSS VSS Note: OPT: Optional by ...
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Absolute Maximum Ratings Supply Voltage ...........................V Input Voltage..............................V I Total ..............................................................100mA OL Total Power Dissipation .....................................500mW Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional ...
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Symbol I I/O Port Sink Current OL1 I I/O Port Source Current OH I PA7 Sink Current OL2 R Pull-high Resistance PH Note: The standby current (I A.C. Characteristics Symbol f System Clock SYS System Clock f HIRC (HIRC) ...
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Symbol System Clock f ERC (ERC) f System Clock (LXT) LXT Timer Input Frequency f TIMER (TCn) t LIRC Oscillator LIRC t External Reset Low Pulse Width RES t System Start-up time Period SST t Interrupt Pulse Width INT ...
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A/D Converter Characteristics Symbol AV Analog Operating Voltage DD A/D Converter Input Voltage DNL Differential Non-Linearity INL Integral Non-Linearity Additional Power Consumption I ADC if A/D Converter is Used t A/D Converter Clock Period AD A/D Converter Conversion Time ...
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System Architecture A key factor in the high-performance features of the Holtek range of microcontrollers is attributed to the inter- nal system architecture. The range of devices take ad- vantage of the usual features found within RISC microcontrollers providing ...
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Program Counter During program execution, the Program Counter is used to keep track of the address of the next instruction to be executed automatically incremented by one each time an instruction is executed except for instructions, such ...
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Program Memory The Program Memory is the location where the user code or program is stored. The device is supplied with One-Time Programmable, OTP, memory where users can program their application code into the device. By using the appropriate ...
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The following diagram illustrates the addressing/data flow of the look-up table: Table Program Example The accompanying example shows how the table pointer and table data is defined and retrieved from the device. This example uses raw table data located ...
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Data Memory The Data Memory is a volatile area of 8-bit wide RAM internal memory and is the location where temporary in- formation is stored. Structure Divided into two sections, the first of these is an area of RAM ...
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Special Function Registers To ensure successful operation of the microcontroller, certain internal registers are implemented in the Data Memory area. These registers ensure correct operation of internal functions such as timers, interrupts, etc., as well as external functions such ...
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Program Counter Low Register - PCL To provide additional program control functions, the low byte of the Program Counter is made accessible to pro- grammers by locating it within the Special Purpose area of the Data Memory. By manipulating ...
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Input/Output Ports and Control Registers Within the area of Special Function Registers, the port PA, PB, etc data I/O registers and their associated con- trol register PAC, PBC, etc play a prominent role. These registers are mapped to specific ...
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CTRL0 Register - HT48R01B-1/HT48R01N-1 Bit Name R/W POR Bit 7 unimplemented, read as 0 Bit 6 PFDCS: PFD clock source selection 0: Timer 0 1: Timer 1 Bit 5~3 unimplemented, read as 0 Bit 2 PFDC: I/O or PFD ...
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Oscillator Various oscillator options offer the user a wide range of functions according to their various application require- ments. The flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and ...
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Internal RC Oscillator - HIRC The internal RC oscillator is a fully integrated system os- cillator requiring no external components. The internal RC oscillator has three fixed frequencies of either 4MHz, 8MHz or 12MHz. Device trimming during the manufacturing ...
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Operating Modes By using the LXT low frequency oscillator in combina- tion with a high frequency oscillator, the system can be selected to operate in a number of different modes. These Modes are Normal, Slow and Sleep. Mode Types ...
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The I/O ports will maintain their present condition. In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared. Standby Current Considerations As the main reason for entering the ...
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Watchdog Timer The Watchdog Timer, also known as the WDT, is pro- vided to inhibit program malfunctions caused by the pro- gram jumping to unknown locations due to certain uncontrollable external events such as electrical noise. Watchdog Timer Operation ...
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WDTS Register Bit Name R/W POR Bit 7~3 : unimplemented, read as 0 Bit 2~0 WS2, WS1, WS0: WDT time-out period selection 000: 2 001: 2 010: 2 011: 2 100: 2 101: 2 110: 2 111: 2 Reset ...
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For applications that operate within an environment where more noise is present the reset circuit shown is recommended. Note recommended that this component is added for added ESD protection ** It is recommended that this component ...
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The following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. ...
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Register ADRL ADRH ADCR ACSR Note: - not implemented u means unchanged x means unknown HT48R01B-1/HT48R01N-1 Register PCL MP0 MP1 ACC TBLP TBLH WDTS STATUS INTC0 INTC1 TMR0 TMR0C TMR1 TMR1C PA PAC PAWK PAPU PB PBC PBPU CTRL0 ...
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Input/Output Ports Holtek microcontrollers offer considerable flexibility on their I/O ports. Most pins can have either an input or out- put designation under user program control. Addi- tionally, as there are pull-high resistors and wake-up software configurations, the user ...
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I/O Port Control Registers Each Port has its own control register, known as PAC, PBC, which controls the input/output configuration. With this control register, each I/O pin with or without pull-high resistors can be reconfigured dynamically un- der software ...
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Rev.1.00 HT46R01B-1/HT46R01N-1 HT48R01B-1/HT48R01N-1 Generic Input/Output Ports PA7 NMOS Input/Output Port PA7 NMOS Input/Output Port 31 June 9, 2011 Datasheet pdf - http://www.DataSheet4U.net/ ...
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I/O Pin Structures The diagrams illustrate the I/O pin internal structures. As the exact logical construction of the I/O pin may differ from these drawings, they are supplied as a guide only to assist with the functional understanding of ...
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Note: If PWM is enabled, then f Rev.1.00 comes from f and the T0S bit will have no effect. TP SYS Clock Structure for Timer/PWM/Time Base 8-bit Timer/Event Counter 0 Structure 8-bit Timer/Event Counter 1 Structure Note: If PWM0 ...
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TMR0C Register Bit Name T0M1 R/W R/W POR Bit 7,6 T0M1, T0M0: Timer0 operation mode selection 00: no mode available 01: event counter mode 10: timer mode 11: pulse width capture mode Bit 5 T0S: timer clock source 0: ...
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TMR1C Register Bit Name T1M1 R/W R/W POR Bit 7,6 T1M1, T1M0: Timer 1 Operation mode selection 00: no mode available 01: event counter mode 10: timer mode 11: pulse width capture mode Bit 5 T1S: timer clock source ...
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Timer Control Registers - TMR0C, TMR1C The flexible features of the Holtek microcontroller Timer/Event Counters enable them to operate in three different modes, the options of which are determined by the contents of their respective control register. The Timer ...
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The interrupt can be dis- abled by ensuring that the Timer/Event Counter Inter- rupt Enable bit in the corresponding Interrupt Control Register, is reset to zero. As the external timer pin is shared with an ...
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PFD Function The Programmable Frequency Divider provides a means of producing a variable frequency output suitable for applications, such as piezo-buzzer driving or other interfaces requiring a precise frequency generator. The Timer/Event Counter overflow signal is the clock source ...
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When the Timer/Event Counter overflows, its corre- sponding interrupt request flag in the interrupt control register will be set. If the Timer/Event Counter interrupt is enabled this will in turn generate an interrupt signal. However irrespective of whether the ...
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Pulse Width Modulator The HT46R01B-1 and HT46R01N-1 devices include 1 8-bit PWM outputs. Useful for the applications such as motor speed control, the PWM function provides out- puts with a fixed frequency but with a duty cycle that can ...
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Rev.1.00 HT46R01B-1/HT46R01N-1 HT48R01B-1/HT48R01N-1 6+2 PWM Mode PWM Register for 6+2 Mode 7+1 PWM Mode PWM Register for 7+1 Mode 41 June 9, 2011 Datasheet pdf - http://www.DataSheet4U.net/ ...
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PWM Output Control The PWM outputs are pin-shared with the I/O pins PA4. To operate as a PWM output and not as an I/O pin, the correct bits must be set in the CTRL0 register. A zero value must ...
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Analog to Digital Converter The need to interface to real world analog signals is a common requirement for many electronic systems. However, to properly process these signals by a microcontroller, they must first be converted into digital signals by ...
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ADRH, ADRL Register Bit 7 Name D11 D10 R POR x unimplemented, read as 0 D11~D0: ADC conversion data ADCR Register Bit Name START R/W R/W POR Bit 7 START: Start the A/D conversion ...
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The ADCR control register also contains the PCR3~PCR0 bits which determine which pins on PA0~PA3 are used as analog inputs for the A/D converter and which pins are to be used as normal I/O pins. Note that if the ...
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A/D Input Pins All of the A/D analog input pins are pin-shared with the I/O pins on Port A. Bits PCR3~PCR0 in the register, de- termine whether the input pins are setup as normal Port A input/output pins or ...
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Rev.1.00 HT46R01B-1/HT46R01N-1 HT48R01B-1/HT48R01N-1 A/D Conversion Timing Ideal A/D Transfer Function 47 June 9, 2011 Datasheet pdf - http://www.DataSheet4U.net/ ...
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A/D Programming Example The following two programming examples illustrate how to setup and implement an A/D conversion. In the first exam- ple, the method of polling the EOCB bit in the ADCR register is used to detect when the ...
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Interrupts Interrupts are an important part of any microcontroller system. When an external event or an internal function such as a Timer/Event Counter or Time Base requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the ...
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When an interrupt request is generated it takes in- struction cycle before the program jumps to the interrupt vector. If the device is in the Sleep Mode and is woken interrupt request then ...
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INTC0 Register Bit Name R/W POR Bit 7 unimplemented, read as 0 Bit 6 T1F: Timer/Event Counter 1 interrupt request flag 0: inactive 1: active Bit 5 T0F: Timer/Event Counter 0 interrupt request flag 0: inactive 1: active Bit ...
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HT48R01B-1/HT48R01N-1 Bit Name R/W POR Bit 7~6 unimplemented, read as 0 Bit 5 TBF: Time Base event interrupt request flag 0: inactive 1: active Bit 4~2 unimplemented, read as 0 Bit 1 TBE: Time base event interrupt enable 0: ...
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Configuration Options Configuration options refer to certain options within the MCU that are programmed into the OTP Program Memory de- vice during the programming process. During the development process, these options are selected using the HT-IDE software development tools. ...
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Instruction Set Introduction ful ope rati microcontroller is its instruction set, which is a set of pro- gram ...
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Bit Operations The ability to provide single bit operations on Data Mem- ory is an extremely flexible feature of all Holtek microcontrollers. This feature is especially useful for output port bit programming where individual bits or port pins can ...
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Mnemonic Rotate RRA [m] Rotate Data Memory right with result in ACC RR [m] Rotate Data Memory right RRCA [m] Rotate Data Memory right through Carry with result in ACC RRC [m] Rotate Data Memory right through Carry RLA ...
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Instruction Definition ADC A,[m] Description Operation Affected flag(s) ADCM A,[m] Description Operation Affected flag(s) ADD A,[m] Description Operation Affected flag(s) ADD A,x Description Operation Affected flag(s) ADDM A,[m] Description Operation Affected flag(s) AND A,[m] Description Operation Affected flag(s) AND ...
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CALL addr Description Operation Affected flag(s) CLR [m] Description Operation Affected flag(s) CLR [m].i Description Operation Affected flag(s) CLR WDT Description Operation Affected flag(s) CLR WDT1 Description Operation Affected flag(s) CLR WDT2 Description Operation Affected flag(s) Rev.1.00 Subroutine call ...
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CPL [m] Description Operation Affected flag(s) CPLA [m] Description Operation Affected flag(s) DAA [m] Description Operation Affected flag(s) DEC [m] Description Operation Affected flag(s) DECA [m] Description Operation Affected flag(s) HALT Description Operation Affected flag(s) Rev.1.00 Complement Data Memory ...
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INC [m] Description Operation Affected flag(s) INCA [m] Description Operation Affected flag(s) JMP addr Description Operation Affected flag(s) MOV A,[m] Description Operation Affected flag(s) MOV A,x Description Operation Affected flag(s) MOV [m],A Description Operation Affected flag(s) NOP Description Operation ...
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OR A,x Description Operation Affected flag(s) ORM A,[m] Description Operation Affected flag(s) RET Description Operation Affected flag(s) RET A,x Description Operation Affected flag(s) RETI Description Operation Affected flag(s) RL [m] Description Operation Affected flag(s) RLA [m] Description Operation Affected ...
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RLC [m] Description Operation Affected flag(s) RLCA [m] Description Operation Affected flag(s) RR [m] Description Operation Affected flag(s) RRA [m] Description Operation Affected flag(s) RRC [m] Description Operation Affected flag(s) RRCA [m] Description Operation Affected flag(s) Rev.1.00 Rotate Data ...
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SBC A,[m] Description Operation Affected flag(s) SBCM A,[m] Description Operation Affected flag(s) SDZ [m] Description Operation Affected flag(s) SDZA [m] Description Operation Affected flag(s) SET [m] Description Operation Affected flag(s) SET [m].i Description Operation Affected flag(s) Rev.1.00 Subtract Data ...
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SIZ [m] Description Operation Affected flag(s) SIZA [m] Description Operation Affected flag(s) SNZ [m].i Description Operation Affected flag(s) SUB A,[m] Description Operation Affected flag(s) SUBM A,[m] Description Operation Affected flag(s) SUB A,x Description Operation Affected flag(s) Rev.1.00 Skip if ...
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SWAP [m] Description Operation Affected flag(s) SWAPA [m] Description Operation Affected flag(s) SZ [m] Description Operation Affected flag(s) SZA [m] Description Operation Affected flag(s) SZ [m].i Description Operation Affected flag(s) TABRDC [m] Description Operation Affected flag(s) TABRDL [m] Description ...
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XOR A,[m] Description Operation Affected flag(s) XORM A,[m] Description Operation Affected flag(s) XOR A,x Description Operation Affected flag(s) Rev.1.00 Logical XOR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR ...
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Package Information Note that the package information provided here is for consultation purposes only. As this information may be updated at regu- lar intervals users are reminded to consult the Holtek website (http://www.holtek.com.tw/english/literature/package.pdf) for the latest version of the ...
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NSOP (150mil) Outline Dimensions MS-012 Symbol Symbol Rev.1.00 HT46R01B-1/HT46R01N-1 HT48R01B-1/HT48R01N-1 Dimensions in inch Min. Nom. 0.228 0.150 0.012 0.386 0.050 ...
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Product Tape and Reel Specifications Reel Dimensions SOP 16N (150mil) Symbol A Reel Outer Diameter B Reel Inner Diameter C Spindle Hole Diameter D Key Slit Width T1 Space Between Flange T2 Reel Thickness Rev.1.00 Description 69 HT46R01B-1/HT46R01N-1 HT48R01B-1/HT48R01N-1 ...
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Carrier Tape Dimensions SOP 16N (150mil) Symbol W Carrier Tape Width P Cavity Pitch E Perforation Position F Cavity to Perforation (Width Direction) D Perforation Diameter D1 Cavity Hole Diameter P0 Perforation Pitch P1 Cavity to Perforation (Length Direction) ...
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... Holtek Semiconductor Inc. (Shenzhen Sales Office) 5F, Unit A, Productivity Building, No.5 Gaoxin M 2nd Road, Nanshan District, Shenzhen, China 518057 Tel: 86-755-8616-9908, 86-755-8616-9308 Fax: 86-755-8616-9722 Holtek Semiconductor (USA), Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, CA 94538 Tel: 1-510-252-9880 Fax: 1-510-252-9885 http://www.holtek.com Copyright 2011 by HOLTEK SEMICONDUCTOR INC ...