HT46801N-1 Holtek Semiconductor, HT46801N-1 Datasheet - Page 52

• Manufacturer Part Number: HT46801N-1
• Description: (HT4xR01x-1) Small Package 8-Bit OTP MCU
• Manufacturer: Holtek Semiconductor

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Timer/Event Counter Interrupt
For a Timer/Event Counter interrupt to occur, the global
interrupt enable bit, EMI, and the corresponding timer
interrupt enable bit, TnE, must first be set. An actual
Timer/Event Counter interrupt will take place when the
Timer/Event Counter request flag, TnF, is set, a situation
that will occur when the relevant Timer/Event Counter
overflows. When the interrupt is enabled, the stack is
not full and a Timer/Event Counter n overflow occurs, a
subroutine call to the relevant timer interrupt vector, will
take place. When the interrupt is serviced, the timer in-
terrupt request flag, TnF, will be automatically reset and
the EMI bit will be automatically cleared to disable other
interrupts.
A/D Converter Interrupt
The HT46R01B-1 and HT46R01N-1 devices include an
A/D interrupt. For an A/D interrupt to occur, the global in-
terrupt enable bit EMI and the corresponding interrupt
enable bit ADE must be first set. An actual A/D interrupt
will take place when the A/D converter request flag ADF
is set, a situation that will occur when an A/D conversion
process has completed. When the interrupt is enabled,
the stack is not full and an A/D conversion process fin-
ishes execution, a subroutine call to the relevant A/D in-
terrupt vector, will take place. When the interrupt is
serviced, the A/D interrupt request flag ADF will be auto-
matically reset and the EMI bit will be automatically
cleared to disable other interrupts. As this interrupt vec-
tor location is shared with other interrupts, to be effec-
tive it must be selected via configuration option.
Time Base Interrupt
For a time base interrupt to occur the global interrupt en-
able bit EMI and the corresponding interrupt enable bit
TBE, must first be set. An actual Time Base interrupt will
take place when the time base request flag TBF is set, a
Rev.1.00
Bit 7~6
Bit 5
Bit 4~2
Bit 1
Bit 0
HT48R01B-1/HT48R01N-1
Name
POR
R/W
Bit
unimplemented, read as 0
TBF: Time Base event interrupt request flag
0: inactive
1: active
unimplemented, read as 0
TBE: Time base event interrupt enable
0: disable
1: enable
unimplemented, read as 0
7
6
R/W
TBF
5
0
52
4
situation that will occur when the Time Base overflows.
When the interrupt is enabled, the stack is not full and a
time base overflow occurs a subroutine call to time base
vector will take place. When the interrupt is serviced, the
time base interrupt flag. TBF will be automatically reset
and the EMI bit will be automatically cleared to disable
other interrupts.
Programming Considerations
By disabling the interrupt enable bits, a requested inter-
rupt can be prevented from being serviced, however,
once an interrupt request flag is set, it will remain in this
condition in the interrupt register until the corresponding
interrupt is serviced or until the request flag is cleared by
a software instruction.
It is recommended that programs do not use the CALL
subroutine instruction within the interrupt subroutine.
Interrupts often occur in an unpredictable manner or
need to be serviced immediately in some applications. If
only one stack is left and the interrupt is not well con-
trolled, the original control sequence will be damaged
once a CALL subroutine is executed in the interrupt
subroutine.
All of these interrupts have the capability of waking up
the processor when in the Sleep Mode.
Only the Program Counter is pushed onto the stack. If
the contents of the register or status register are altered
by the interrupt service program, which may corrupt the
desired control sequence, then the contents should be
saved in advance.
3
HT46R01B-1/HT46R01N-1
HT48R01B-1/HT48R01N-1
2
TBE
R/W
1
0
June 9, 2011
0
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