HT46C47 Holtek Semiconductor, HT46C47 Datasheet - Page 8

• Manufacturer Part Number: HT46C47
• Description: (HT46C46 / HT46C47) Cost-Effective A/D Type 8-Bit MCU
• Manufacturer: Holtek Semiconductor

Stack Register - STACK
This is a special part of the memory which is used to
save the contents of the program counter only. The
stack is organized into 4 levels for the HT46R46/
HT46C46 or 6 levels for the HT46R47/HT46C47 and
are neither part of the data nor part of the program
space, and is neither readable nor writeable. The acti-
vated level is indexed by the stack pointer (SP) and is
neither readable nor writeable. At a subroutine call or in-
terrupt acknowledgment, the contents of the program
counter are pushed onto the stack. At the end of a sub-
routine or an interrupt routine, signaled by a return in-
struction (RET or RETI), the program counter is restored
to its previous value from the stack. After a chip reset,
the SP will point to the top of the stack.
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag will be recorded but the
acknowledgment will be inhibited. When the stack
pointer is decremented (by RET or RETI), the interrupt
will be serviced. This feature prevents stack overflow al-
lowing the programmer to use the structure more easily.
In a similar case, if the stack is full and a CALL is sub-
sequently executed, stack overflow occurs and the first
e nt r y wi l l be lo st (o nl y t he mo st re ce nt 4
(HT46R47/HT46C46) or 6 (HT46R47/HT46C47) return
addresses are stored).
Data Memory - RAM
The data memory is designed with 84 8 bits
(HT46R46/HT46C46) or 85 8 bits (HT46R47/HT46C47).
The data memory is divided into two functional groups:
special function registers and general purpose data
memory (64 8). Most are read/write, but some are
read only.
The special function registers include the indirect ad-
dressing register (00H), timer/event counter
(TMR;0DH), timer/event counter control register
(TMRC;0EH), program counter lower-order byte regis-
ter (PCL;06H), memory pointer register (MP;01H), ac-
cumulator (ACC;05H), table pointer (TBLP;07H), table
higher-order byte register (TBLH;08H), status register
(STATUS;0AH), interrupt control register (INTC;0BH),
PWM data register (PWM;1AH), the A/D result register
(ADR;21H) for the HT46R46/HT46C46, the A/D result
lower-order byte register (ADRL;20H) for the
HT46R47/HT46C47, the A/D result higher-order byte
Rev. 1.00
Errors can occur. In other words, using the table read
instruction in the main routine and the ISR simulta-
neously should be avoided. However, if the table read
instruction has to be applied in both the main routine
and the ISR, the interrupt is supposed to be disabled
prior to the table read instruction. It will not be enabled
until the TBLH has been backed up. All table related
instructions require two cycles to complete the opera-
tion. These areas may function as normal program
memory depending upon the requirements.
HT46R46/HT46C46/HT46R47/HT46C47
8
register (ADRH;21H) for the HT46R47/HT46C47, the
A/D control register (ADCR;22H), the A/D clock setting
register (ACSR;23H), I/O registers (PA;12H, PB;14H,
PD;18H) and I/O control registers (PAC;13H,
PBC;15H, PDC;19H). The remaining space before the
40H is reserved for future expanded usage and reading
these locations will get 00H . The general purpose
data memory, addressed from 40H to 7FH, is used for
data and control information under instruction com-
mands.
All of the data memory areas can handle arithmetic,
logic, increment, decrement and rotate operations di-
rectly. Except for some dedicated bits, each bit in the
data memory can be set and reset by SET [m].i and
memory pointer register (MP;01H).
CLR [m].i . They are also indirectly accessible through
RAM Mapping for the HT46R46/HT46C46
December 28, 2004