HT46R4A Holtek Semiconductor, HT46R4A Datasheet
HT46R4A
Related parts for HT46R4A
HT46R4A Summary of contents
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... As is the case with all Holtek microcontroller devices, the HT46R4A is fully supported by a full suite of profesional hardware and software tools, containing comprehensive features to ensure user applications are designed and debugged in as short a time as possible. ...
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... Block Diagram www.datasheet4u.com Pin Assignment Rev. 1.00 2 November 28, 2007 HT46R4A ...
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... OSC2 can be used to measure the system clock at 1/4 frequency. Schmitt Trigger reset input. Active low. Positive power supply Negative power supply, ground 0. +6.0V Storage Temperature ............................ 125 0. +0.3V Operating Temperature........................... HT46R4A Description Total............................................................ 100mA November 28, 2007 ...
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... No load, f ADC disable 5V No load ADC disable 3V No load, system HALT load, system HALT 5V V =0. =0. =0. =0. HT46R4A Min. Typ. Max. 2.2 5.5 3.3 5.5 0.6 1.5 =4MHz SYS 2 4 0.8 1.5 =4MHz SYS 2.5 4 =8MHz SYS 0. 0. ...
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... A/D Clock Period AD t A/D Conversion Time ADC t A/D Sampling Time ADCS Note: *t =1/f SYS SYS Rev. 1.00 Test Conditions Parameter V Conditions DD 2.2V~5.5V 3.3V~5.5V 2.2V~5.5V 3.3V~5. Wake-up from HALT 5 HT46R4A Ta=25 C Min. Typ. Max. Unit 400 4000 kHz 400 8000 kHz 0 4000 kHz 0 8000 kHz 45 90 180 130 s 15 ...
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... JMP or CALL that demand a jump to a non-consecutive Program Memory address. However, it must be noted that only the lower 8 bits, known as the Program Counter Low Register, are directly address- able by user. System Clocking and Pipelining Instruction Fetching 6 HT46R4A /4 with a 1:3 high/low duty cycle. November 28, 2007 ...
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... Program Counter + 2 PC11 PC10 PC9 PC8 @7 @6 #11 # S11 S10 Program Counter 7 HT46R4A ...
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... Program Memory will be transferred to the user de- fined Data Memory register [m] as specified in the in- struction. The higher order table data byte from the Program Memory will be transferred to the TBLH special register. Any unused bits in this transferred higher order byte will be read November 28, 2007 HT46R4A ...
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... TBLH ; sets initial address of last page Table Location Bits b10 PC10 PC9 PC8 @ Table Location 9 HT46R4A November 28, 2007 ...
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... Spe- cial Function Register section. Note that for locations that are unused, any read instruction to these addresses will return the value 00H . Special Purpose Data Memory 10 November 28, 2007 HT46R4A ...
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... Accumulator loaded with first RAM address mov mp,a ; setup memory pointer with first RAM address clr IAR ; clear the data at address defined by MP inc mp ; increment memory pointer sdz block ; check if last memory location has been cleared jmp loop 11 HT46R4A November 28, 2007 ...
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... OV is cleared. PDF is cleared by a system power-up or executing the CLR WDT instruction. PDF is set by executing the HALT instruction cleared by a system power-up or executing the CLR WDT or HALT instruction set by a WDT time-out. Status Register 12 HT46R4A November 28, 2007 ...
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... The channel selection and configuration of the A/D con- verter is setup via the control register ADCR while the A/D clock frequency is defined by the clock source reg- ister, ACSR. 13 November 28, 2007 HT46R4A ...
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... PDC, must setup the pin as an output to enable the PWM output. If the PDC port control register has setup the pin as an in- put, then the pin will function as a normal logic input 14 November 28, 2007 HT46R4A timer ...
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... The following diagrams illustrate the I/O pin internal structures. As the exact logical construction of the I/O pin may differ from these drawings, they are supplied as a guide only to assist with the functional understanding of the I/O pins. Non-pin-shared Function Input/Output Ports PA4/PA5 Input/Output Ports 15 HT46R4A November 28, 2007 ...
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... Rev. 1.00 PA3/PFD and PD/PWM Input/Output Ports PB Input/Output Ports 16 HT46R4A November 28, 2007 ...
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... However, if the counter is enabled and counting, any new data written into the preload register during this period will remain in the preload register and will only be written into the ac- tual counter the next time an overflow occurs. 17 November 28, 2007 HT46R4A ...
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... ET0I and ET1I bits of the respective interrupt register are reset to zero. It should be noted that a timer overflow is one of the interrupt and wake-up sources. 18 HT46R4A November 28, 2007 ...
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... Rev. 1.00 Timer/Event Counter 0 Control Register Timer/Event Counter 1 Control Register 19 HT46R4A November 28, 2007 ...
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... T0M1/T0M0 or T1M1/T1M0 bits place the Timer/Event Counter in the pulse width mea- suring mode, the second is to ensure that the port con- trol register configures the pin as an input. It should be noted that a timer overflow is one of the interrupt and wake-up sources. 20 HT46R4A November 28, 2007 ...
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... For the pulse width measurement mode, the internal system clock is also used as the timer clock source but the timer will only run when the correct logic condition appears on the external 21 HT46R4A November 28, 2007 ...
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... Timer/Event Counter interrupt vector ; jump here when Timer/Event Counter 0 overflows ; main program ; setup Timer preload value ; setup Timer control register ; timer mode and prescaler set enable Master and Timer/Event Counter 0 interrupt ; start Timer/Event Counter 0 - note mode bits must be previously setup 22 HT46R4A November 28, 2007 ...
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... PWM function, but a 1 has been written to its corresponding bit in the PDC control register to configure the pin as an input, then the pin can still function as a normal input line, with pull-high resistor options. 23 HT46R4A DC Parameter AC (0~3) (Duty Cycle i< ...
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... Rev. 1.00 6+2 PWM Mode Pulse Width Modulation Registers ; setup PWM0 value of 100 decimal which is 64H ; setup pin PD0 as an output ; PD.0=1; enable the PWM0 output ; disable the PWM0 output - PD0 will remain low 24 HT46R4A November 28, 2007 ...
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... AN0, AN1, AN2, AN3, AN4 and AN5 will all be set as analog inputs. Note that if the PCR2~PCR0 bits are all set to zero, then all the Port B pins will be setup as normal I/Os and the internal A/D converter circuitry will be powered off to reduce the power consumption. A/D Converter Structure 25 HT46R4A ...
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... A/D Clock Period. A/D Converter Control Register A/D Converter Clock Source Register 26 HT46R4A , is first divided by a division SYS care must be taken for system November 28, 2007 ...
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... When this occurs the A/D data registers ADRL and ADRH can be read to obtain the conversion value alternative method if the in- terrupts are enabled and the stack is not full, the pro- gram can wait for an A/D interrupt to occur. Note: 27 HT46R4A ) AD ADCS1, ADCS0=10 ADCS1, ADCS0=11 (f /32) ...
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... ACSR register to select f ; the A/D clock a,00100000B ; setup ADCR register to configure Port PB0~PB3 ; as A/D inputs ADCR,a ; and select AN0 to be connected to the A/D ; converter : : ; As the Port B channel bits have changed the ; following START ; signal (0-1-0) must be issued within 10 ; instruction cycles : 28 HT46R4A /8 as SYS November 28, 2007 ...
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... STATUS,a ; restore STATUS from user defined memory a,acc_stack ; restore ACC from user defined memory 29 HT46R4A November 28, 2007 ...
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... EMI bit should be set after entering the rou- tine, to allow interrupt nesting. If the stack is full, the in- terrupt request will not be acknowledged, even if the related interrupt is enabled, until the Stack Pointer is decremented. If immediate service is desired, the stack must be prevented from becoming full. Ideal A/D Transfer Function 30 HT46R4A November 28, 2007 ...
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... EIF; bit 4 of INTC0 will be auto- matically reset and the EMI bit will be automatically cleared to disable other interrupts. Note that any pull-high resistor configuration options on this pin will remain valid even if the pin is used as an external interrupt input. 31 HT46R4A November 28, 2007 ...
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... Another type of reset is when the Watchdog Timer overflows and resets the microcontroller. All types of re- set operations result in different register conditions be- ing setup. 32 HT46R4A November 28, 2007 ...
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... LVR will ignore the low supply voltage and will not perform a reset function. The actual V lected via configuration options. 33 HT46R4A Enhanced Reset Circuit RES Reset Timing Chart LVR such as might occur when ...
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... The following table describes how each type of reset affects each of the microcontroller internal registers. RESET Conditions 34 HT46R4A Item Condition After RESET Reset to zero All interrupts will be disabled Clear after reset, WDT begins ...
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... HT46R4A WDT Time-out WDT Time-out (Normal Operation) (HALT ...
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... For the value of the external resistor R please refer to the Appendix section for typical RC Os- cillator vs. Temperature and V characteristics graph- DD ics. 36 November 28, 2007 HT46R4A C2 CL* TBD TBD TBD TBD TBD TBD TBD ...
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... Each pin on Port A can be setup via an individual config- uration option to permit a negative transition on the pin to wake-up the system. When a Port A pin wake-up oc- curs, the program will resume execution at the instruc- tion following the HALT instruction. 37 November 28, 2007 HT46R4A ...
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... CLR WDT2 instruction will clear the WDT. Similarly after the CLR WDT2 instruction has been executed, only a successive CLR WDT1 instruction can clear the Watchdog Timer. Watchdog Timer 38 HT46R4A / further di- SYS . As the clear instruction S November 28, 2007 ...
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... Watchdog Timer function: enable or disable 3 CLRWDT instructions instructions 4 System oscillator: Crystal PA, PB, PC and PD: pull-high enable or disable 6 PWM0, PWM1: enable or disable 7 PA0~PA7: wake-up enable or disable - bit option 8 PFD: normal I/O or PFD output 9 LVR function: enable or disable Rev. 1.00 Options /4 SYS 39 November 28, 2007 HT46R4A ...
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... Application Circuits www.datasheet4u.com Rev. 1.00 40 November 28, 2007 HT46R4A ...
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... These instructions are the key to decision making and branching within the pro- gram perhaps determined by the condition of certain in- put switches or by the condition of internal data bits. 41 November 28, 2007 HT46R4A ...
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... Table conventions: x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address Description 42 HT46R4A Cycles Flag Affected AC, OV Note AC AC ...
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... For the CLR WDT1 and CLR WDT2 instructions the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after both CLR WDT1 and CLR WDT2 instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged. Rev. 1.00 Description 43 HT46R4A Cycles Flag Affected 1 None Note 1 ...
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... Data in the Accumulator and the specified immediate data perform a bitwise logical AND operation. The result is stored in the Accumulator. ACC ACC AND x Z Logical AND ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical AND op- eration. The result is stored in the Data Memory. [m] ACC AND [ HT46R4A November 28, 2007 ...
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... The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunc- tion with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Re- petitively executing this instruction without alternately executing CLR WDT1 will have no effect. WDT cleared TO 0 PDF 0 TO, PDF 45 HT46R4A November 28, 2007 ...
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... This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared PDF 1 TO, PDF 46 HT46R4A November 28, 2007 ...
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... None No operation No operation is performed. Execution continues with the next instruction. No operation None Logical OR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical OR oper- ation. The result is stored in the Accumulator. ACC ACC OR [ HT46R4A November 28, 2007 ...
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... Rotate Data Memory left with result in ACC The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory re- main unchanged. ACC.(i+1) [m]. 0~6) ACC.0 [m].7 None 48 HT46R4A November 28, 2007 ...
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... Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 re- places the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i [m].(i+1 0~6) ACC [m]. HT46R4A November 28, 2007 ...
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... ACC [m] 1 Skip if ACC = 0 None Set Data Memory Each bit of the specified Data Memory is set to 1. [m] FFH None Set bit of Data Memory Bit i of the specified Data Memory is set to 1. [m].i 1 None 50 HT46R4A November 28, 2007 ...
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... The immediate data specified by the code is subtracted from the contents of the Accumu- lator. The result is stored in the Accumulator. Note that if the result of subtraction is nega- tive, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ACC x OV HT46R4A November 28, 2007 ...
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... Read table (last page) to TBLH and Data Memory The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] program code (low byte) TBLH program code (high byte) None 52 HT46R4A November 28, 2007 ...
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... Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR op- eration. The result is stored in the Data Memory. [m] ACC XOR [m] Z Logical XOR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ACC XOR HT46R4A November 28, 2007 ...
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... Package Information 28-pin SKDIP (300mil) Outline Dimensions www.datasheet4u.com Symbol Rev. 1.00 Dimensions in mil Min. Nom. 1375 278 125 125 16 50 100 295 330 0 54 HT46R4A Max. 1395 298 135 145 20 70 315 375 15 November 28, 2007 ...
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... SOP (300mil) Outline Dimensions www.datasheet4u.com Symbol Rev. 1.00 Dimensions in mil Min. Nom. 394 290 14 697 HT46R4A Max. 419 300 20 713 104 November 28, 2007 ...
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... DIP (600mil) Outline Dimensions www.datasheet4u.com Symbol Rev. 1.00 Dimensions in mil Min. Nom. 1635 535 145 125 16 50 100 595 635 0 56 HT46R4A Max. 1665 555 155 145 20 70 615 670 15 November 28, 2007 ...
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... QFP (10´10) Outline Dimensions www.datasheet4u.com Symbol Rev. 1.00 Dimensions in mm Min. Nom. 13 9.9 13 9.9 0.8 0.3 1.9 0.25 0.73 0.1 0 HT46R4A Max. 13.4 10.1 13.4 10.1 2.2 2.7 0.5 0.93 0.2 7 November 28, 2007 ...
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... Product Tape and Reel Specifications Reel Dimensions www.datasheet4u.com SOP 28W (300mil) Symbol A Reel Outer Diameter B Reel Inner Diameter C Spindle Hole Diameter D Key Slit Width T1 Space Between Flange T2 Reel Thickness Rev. 1.00 Description 58 HT46R4A Dimensions in mm 330 1 62 1.5 13+0.5 0.2 2 0.5 24.8+0.3 0.2 30.2 0.2 November 28, 2007 ...
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... Carrier Tape Width P Cavity Pitch E Perforation Position F Cavity to Perforation (Width Direction) D Perforation Diameter D1 Cavity Hole Diameter P0 Perforation Pitch P1 Cavity to Perforation (Length Direction) A0 Cavity Length B0 Cavity Width K0 Cavity Depth t Carrier Tape Thickness C Cover Tape Width Rev. 1.00 Description 59 HT46R4A Dimensions 0.3 12 0.1 1.75 0.1 11.5 0.1 1.5+0.1 1.5+0.25 4 0.1 2 0.1 10.85 0.1 18.34 0.1 2.97 0.1 0.35 0.01 21.3 November 28, 2007 ...
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... Holtek s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.00 60 November 28, 2007 HT46R4A ...