HT46R4A Holtek Semiconductor, HT46R4A Datasheet - Page 26

• Manufacturer Part Number: HT46R4A
• Description: Cost-Effective A/D Type 8-Bit MCU
• Manufacturer: Holtek Semiconductor

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The START bit in the ADCR register is used to start and
reset the A/D converter. When the microcontroller sets
this bit from low to high and then low again, an analog to
digital conversion cycle will be initiated. When the
START bit is brought from low to high but not low again,
the EOCB bit in the ADCR register will be set to a 1
and the analog to digital converter will be reset. It is the
START bit that is used to control the overall on/off opera-
tion of the internal analog to digital converter.
The EOCB bit in the ADCR register is used to indicate
when the analog to digital conversion process is com-
plete. This bit will be automatically set to 0 by the
microcontroller after a conversion cycle has ended. In
addition, the corresponding A/D interrupt request flag
will be set in the interrupt control register, and if the inter-
rupts are enabled, an appropriate internal interrupt sig-
nal will be generated. This A/D internal interrupt signal
will direct the program flow to the associated A/D inter-
nal interrupt address for processing. If the A/D internal
interrupt is disabled, the microcontroller can be used to
poll the EOCB bit in the ADCR register to check whether
it has been cleared as an alternative method of detect-
ing the end of an A/D conversion cycle.
Rev. 1.00
A/D Converter Clock Source Register
A/D Converter Control Register
26
A/D Converter Clock Source Register - ACSR
The clock source for the A/D converter, which originates
from the system clock f
ratio, the value of which is determined by the ADCS1
and ADCS0 bits in the ACSR register.
Although the A/D clock source is determined by the sys-
tem clock f
some limitations on the maximum A/D clock source speed
that can be selected. As the minimum value of permissible
A/D clock period, t
clock speeds in excess of 2MHz. For system clock speeds
in excess of 2MHz, the ADCS1 and ADCS0 bits should not
be set to 00 . Doing so will give A/D clock periods that are
less than the minimum A/D clock period which may result
in inaccurate A/D conversion values. Refer to the following
table for examples, where values marked with an asterisk
* show where, depending upon the device, special care
must be taken, as the values may be less than the speci-
fied minimum A/D Clock Period.
SYS
, and by bits ADCS1 and ADCS0, there are
AD
is 1 s, care must be taken for system
SYS
, is first divided by a division
November 28, 2007
HT46R4A