HT46R52A Holtek Semiconductor, HT46R52A Datasheet - Page 15

• Manufacturer Part Number: HT46R52A
• Description: (HT46R51A / HT46R52A) A/D Type 8-Bit OTP MCU
• Manufacturer: Holtek Semiconductor

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Input/Output Ports
There are 14 bidirectional input/output lines in the
microcontroller, labeled as PA, PB and PD, which are
mapped to the data memory of [12H], [14H] and [18H]
respectively. All of these I/O ports can be used for input
and output operations. For input operation, these ports
are non-latching, that is, the inputs must be ready at the
T2 rising edge of instruction MOV A,[m] (m=12H, 14H
or 18H). For output operation, all the data is latched and
remains unchanged until the output latch is rewritten.
Each I/O line has its own control register (PAC, PBC,
PDC) to control the input/output configuration. With this
control register, CMOS output or Schmitt trigger input
with or without pull-high resistor structures can be re-
configured dynamically under software control. To func-
tion as an input, the corresponding latch of the control
register must write 1 . The input source also depends
on the control register. If the control register bit is 1 ,
the input will read the pad state. If the control register bit
is 0 , the contents of the latches will move to the inter-
nal bus. The latter is possible in the read-modify-write
instruction.
For output function, CMOS is the only configuration.
These control registers are mapped to locations 13H,
15H and 19H.
After a chip reset, these input/output lines remain at high
levels or floating state (dependent on pull-high options).
Each bit of these input/output latches can be set or
cleared by SET [m].i and CLR [m].i (m=12H, 14H or
18H) instructions.
Rev. 1.00
Input/Output Ports
15
Some instructions first input data and then follow the
output operations. For example, SET [m].i , CLR
[m].i , CPL [m] , CPLA [m] read the entire port states
into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or the accumulator.
Each line of port A has the capability of waking-up the
device. Each I/O port has a pull-high option. Once the
pull-high option is selected, the I/O port has a pull-high
resistor, otherwise, there s none. Take note that a non-
pull-high I/O port operating in input mode will cause a
floating state.
The PA3, PA4 and PA5 are pin-shared with PFD, TMR
and INT pins respectively.
If the PFD option is selected, the output signal in output
mode of PA3 will be the PFD signal generated by the
timer/event counter overflow signal. The input mode al-
ways remain in its original functions. Once the PFD op-
tion is selected, the PFD output signal is controlled by
the PA3 data register only. The I/O functions of PA3 are
shown below.
Note:
Mode
PA3
I/O
The PFD frequency is the timer/event counter
overflow frequency divided by 2.
(Normal)
Logical
Input
I/P
HT46R51A/HT46R52A
(Normal)
Logical
Output
O/P
Logical
(PFD)
Input
I/P
August 24, 2006
(Timer on)
(PFD)
PFD
O/P