HT48CA3 Holtek Semiconductor Inc, HT48CA3 Datasheet - Page 14

• Manufacturer Part Number: HT48CA3
• Description: 8-Bit Remote Type MCU
• Manufacturer: Holtek Semiconductor Inc

Timer/Event Counter 1 preload register. The
Timer/Event Counter 1 will still operate until the overflow
occurs (a Timer/Event Counter 1 reloading will occur at
the same time).
When the Timer/Event Counter 1 (reading TMR1H) is
read, the clock will be blocked to avoid errors. As this
may results in a counting error, this must be taken into
consideration by the programmer.
The definitions of the TMR1C are as shown.
Input/Output Ports
There are 23 bi-directional input/output lines in the mi-
cro-controller, labeled from PA to PC and PF, which are
mapped to the data memory of [12H], [14H], [16H] and
[1CH], respectively. All of these I/O ports can be used as
input and output operations. For input operation, these
ports are non-latching, that is, the inputs must be ready
at the T2 rising edge of instruction MOV A,[m] (m =
12H, 14H, 16H or 1CH). For output operation, all the
data is latched and remains unchanged until the output
latch is rewritten.
Each I/O line has its own control register (PAC, PBC,
PCC, PFC) to control the input/output configuration.
With this control register, CMOS output or Schmitt trig-
ger input with or without (depends on options) pull-high
resistor structures can be reconfigured dynamically (i.e.,
on-the fly) under software control. To function as an in-
put, the corresponding latch of the control register has to
be set as 1 . The pull-high resistor (if the pull-high re-
sistor is enabled) will be exhibited automatically. The in-
put sources also depends on the control register. If the
control register bit is 1 , the input will read the pad state
( mov and read-modify-write instructions”). If the con-
trol register bit is 0, the contents of the latches will move
to internal data bus ( mov and read-modify-write in-
Rev. 1.40
(TMR1C)
TE
TON
TM0
TM1
Label
Bits
0~2 Unused bit, read as 0
3
4
5
6
7
To define the active edge of TMR1
pin input signal
(0/1: active on low to high/high to low)
To enable/disable timer 1 counting
(0/1: disabled/enabled)
Unused bit, read as 0
To define the operating mode
01=Event count mode (external
clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
TMR1C register
Function
14
structions). The input paths (pad state or latches) of
read-modify-write instructions are dependent on the
control register bits. For output function, CMOS is the
only configuration. These control registers are mapped
to locations 13H, 15H, 17H and 1DH.
After a chip reset, these input/output lines stay at high
levels (pull-high options) or floating state (non-pull-high
options). Each bit of these input/output latches can be
set or cleared by SET [m].i (m = 12H, 14H, 16H or
1CH) instructions. Some instructions first input data and
then follow the output operations. For example, SET
[m].i , CLR [m].i , CPLA [m] read the entire port
states into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or the accumulator.
Each line of port A has the capability of waking-up the
device. The highest 2 bits of port C and 7 bits of port F
are not physically implemented; on reading them a 0 is
returned whereas writing then results in a no-operation.
Pull-high resistors of each port are decided by a option
bit.
The PB0 is pin-shared with PFD signal, respectively. If
the PFD option is selected, the output signal in output
mode of PB0 will be the PFD signal. The input mode al-
ways remain its original functions. The PF0 and PC0 are
pin-shared with INT and TMR 0. The INT signal is di-
rectly connected to PF0. The PFD output signal (in out-
put mode) are controlled by the PB0 data register only.
The truth table of PB0/PFD is listed below.
Note:
Bank Pointer
There is a bank pointer used to control the program flow
to go to any banks. A bank contains 8K 16 address
space. The contents of bank pointer are load into pro-
gram counter when the JMP or CALL instruction is exe-
cuted. The program counter is a 15-bit register whose
contents are used to specify the executed instruction
addresses.
When calling a subroutine or an interrupt event occur-
ring, the contents of the program counter are save into
stack registers. If a returning from subroutine occurs,
the contents of the program counter will restore from
stack registers.
PBC (15H) Bit0
PB0/PFD Option
PB0 (14H) Bit0
PB0 Pad Status
I: Input; O: Output; D: Data
x
x
I
I
PB0
O
D
D
PFD
HT48CA3
O
0
0
July 16, 2003
PFD
PFD
O
1