LM1253AN National Semiconductor, LM1253AN Datasheet - Page 46

• Manufacturer Part Number: LM1253AN
• Description: Monolithic Triple 180 MHz I2C CRT Pre-amp With Integrated Analog On Screen Display (OSD) Generator
• Manufacturer: National Semiconductor

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Control Register Definitions
Software Reset and Test Control Register (I
REGISTER NAME: SRTSTCTRL (843Fh)
Bit 7
Bit 0:
Bits 1–5: Reserved
Bit 6:
Bit 7:
ATTRIBUTE TABLE AND ENHANCED FEATURES
Each display character and SL in the Display Page RAM will have a 4-bit Attribute Table entry associated with it. The user should
note that two-color display characters and four-color display characters use two different Attribute Tables, effectively providing
16 attributes for two-color display characters and 16 attributes for four-color display characters.
For two-color characters the attribute contains the code for the 9-bit foreground color (Color 2), the code for the 9-bit background
color (Color 1), and the character’s enhanced features (Button Box, Blinking, Heavy Box, Shadowing, bordering, etc.).
For four-color characters the attribute contains the code for the 9-bit Color 1, the code for the 9-bit Color 2, the code for the 9-bit
Color 3, the code for the 9-bit Color 4 and the character’s enhanced features (Button Box, Blinking, Heavy Box, Shadowing, bor-
dering, etc.).
TWO-COLOR ATTRIBUTE FORMAT
REGISTER NAME: ATT2C3n (8443h +(n*4)), ATT2C2n (8442h +(n*4)),
Bit 31
REGISTER NAME: ATT2C1n (8441h +(n*4)), ATT2C0n (8440h +(n*4)),
Bit 15
Bits 8–0:
Bits 17–9:
C2B0
RSV
RSV
where n = attribute code (See Table 13 )
where n = attribute code (See Table 13 )
C2G2
RSV
Software Reset. Setting this bit causes a software reset. All registers (except this one) are loaded with their default val-
ues. All operations currently in progress are aborted (except for I
when the reset has been completed.
Auto Increment Disable. Setting this bit to one disables the automatic address increment feature of the I
cess protocol.
Reserved
AID
Color 1. These nine bits indicate the value of the color to be displayed as color 1. This is considered to be the back-
ground color and is displayed when the corresponding pixel data bit is a zero.
Color 2. These nine bits indicate the value of the color to be displayed as color 2. This is considered to be the fore-
ground color and is displayed when the corresponding pixel data bit is a one.
C2G1
RSV
RSV
C2G0
RSV
RSV
Note: These settings are valid when R28 = 6.2k, C23 = 0.1 µF,
C33 = 2.2 nF.
Frequency
100 kHz
30 kHz
35 kHz
40 kHz
45 kHz
50 kHz
55 kHz
60 kHz
65 kHz
70 kHz
75 kHz
80 kHz
85 kHz
90 kHz
95 kHz
C2R2
RSV
RSV
TABLE 12. PLL Setting (Register 843Eh)
C2R1
RSV
2
RSV
C address 843Fh).
(Continued)
Range
C2R0
RSV
1
1
2
2
2
2
2
2
3
3
3
3
3
3
3
RSV
Bit 24
C1B2
RSV
Bit 8
46
SRST
Value for Register 843Eh
Bit 23
Bit 7
C1B1
Bit 0
RSV
C1B0
RSV
2
C transactions). This bit automatically clears itself
01h
01h
02h
02h
02h
02h
02h
02h
03h
03h
03h
03h
03h
03h
03h
EFB3
C1G2
EFB2
C1G1
EFB1
C1G0
EFB0
C1R2
2
C2B2
C1R1
C register ac-
C1R0
C2B1
Bit 16
Bit 0