PDSP1601 Mitel Networks Corporation, PDSP1601 Datasheet - Page 4

• Manufacturer Part Number: PDSP1601
• Description: ALU and Barrel Shifter
• Manufacturer: Mitel Networks Corporation

PDSP1601/PDSP1601A
FUNCTIONAL DESCRIPTION
Barrel Shifter and the two Register Files.
The ALU
Data will fall through from the selected register through the A
or B input MUXs and the ALU to the ALU output register file in
50ns for the PDSP1601A (100ns for the PDSP1601).
will not start executing until the rising edge of CLK latches the
instruction into the device.
a carry out to the CO output. Additionally, at the end of each
cycle, the carry out from the ALU is loaded into an internal 1
bit register, so that it is available as an input to the ALU on the
next cycle.
operations are supported. (See MULTICYCLE CASCADE
OPERATIONS).
BFP Flag
may be programmed to become active at any one of four
conditions. Two of these conditions are intended to support
Block Floating Point operations, in that they provide flags
indicating that the ALU result is within a factor of two or four of
overflowing the 16 bit number range. For multiprecision
operations the flag is only valid whilst the most significant 16
bit byte is being processed. In this manner the BFP flag may
be used over any extended word width.
condition or a zero result. For the overflow condition to be
4
The PDSP1601 contains four main blocks: the ALU, the
The ALU supports 32 instructions as detailed in Table 1.
The inputs to the ALU are selected by the A and B MUXs.
The ALU instructions are latched, such that the instruction
The ALU accepts a carry in from the CI input and supplies
The ALU has a user programmable BFP flag. This flag
The remaining two conditions detect either an overflow
In the manner, multicycle, multiprecision
CO
BFP
A INPUT
A MUX
A REG
A
LEFT REG.
16
ALU REG FILE
MSA0-1
CEA
ALU
RIGHT REG.
2
B MUX
Fig.2 PDSP1601 block diagram
B
RAD-2
IA0-4
CI
3
MSB
5
OE
C MUX
COUT
16
active the ALU result must have overflowed into the 16th (sign)
bit, (this flag is only valid whilst the most significant 16 bit byte
is being processed). The zero condition is active if the result
from the ALU is equal to zero. For multiprecision operations
the zero flag must be active for all of the 16 bit bytes of an
extended word.
SBFXX instructions (see Table 1). During the execution of any
of these four instructions, the output of the ALU is forced to
zero.
Multicycle/Cascade Operation
options for each arithemtic operation.
arithmetic, requiring a one to be added to the LSB for all
subtract operations. The instructions set includes instructions
that will force a one into the LSB, e.g. MIAX1, AMBX1, BMAX1
(see Table 1).
byte of any subtract operation.
multicycling a single device to extend the arithmetic precision.
Should the user cascade multiple devices, then the cascade
arithmetic instructions using the external CI input should be
employed for all but the least significant 16 bit byte, e.g. MIACI,
APBCI, BMACI (see Table 1).
Multicycle Arithmetic instructions, using the internally
registered CO bit should be employed for all but the least
significant 16 bit byte, e.g. MIACO, APBCO, AMBCO,
BMACO (see Table 1).
MSC
The BFP flag is programmed by executing on of the four
The ALU arithmetic instructions contain two or three
The ALU is designed to operate with two's complement
These instructions are used for the least significant 16 bit
The user has an option of cascading multiple devices, or
Should the user multicycle a single device, then the
3
RS0-2
LEFT REG.
SHIFTER REG FILE
BARREL SHIFTER
S MUX
B INPUT
B REG
RIGHT REG.
16
CEB
MSS
CONTROL
SHIFT
SVOE
IS0-3
SV0-3