PDSP1601 Mitel Networks Corporation, PDSP1601 Datasheet - Page 8

• Manufacturer Part Number: PDSP1601
• Description: ALU and Barrel Shifter
• Manufacturer: Mitel Networks Corporation

PDSP1601/PDSP1601A
The Register Files
containing two 16 bit registers and each supporting 8
instructions (see Table 4). The instructions for the ALU
register file and the Barrel Shifter Register file are the same.
the Barrel Shifter, and are loaded into the Register files on the
rising edge of CLK.
instruction will not start executing until the rising edge of the
8
There are two on-chip register files (ALU and Shifter), each
The Inputs to the register files come from either the ALU or
The register file instructions are latched such that the
Inst
Inst
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
MNEMONICS
LXXYY
LBOXX Load Both Registers, XX = Source of Output
NOPXX No Load Operation,
RA2-RA0
RA2-RA0
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
Table 4 ALU and shift register instructions mnemonics
Load XX = Target,
SHIFTER REGISTER INSTRUCTIONS
ALU REGISTER INSTRUCTIONS
Mnemonic
Mnemonic
NOPRR
NOPRR
NOPPS
NOPPS
LRRRR
NOPLR
LRRRR
NOPLR
LLRRR
LRRLR
LLRRR
LRRLR
LBRLR
LLRLR
LBRLR
LLRLR
Load Left Reg Output Right Reg
Load Right Reg Output Left Reg
Load Left Register, Output Left Reg
Load Right Register, Output Right Reg
Load Both Registers, Output Left Reg
No Load Operation, Output Right Reg
No Load Operation, Output Left Reg
No Load Operation, Pass ALU Result
Load Left Reg Output Right Reg
Load Right Reg Output Left Reg
Load Left Register, Output Left Reg
Load Right Register, Output Right Reg
Load Both Registers, Output Left Reg
No Load Operation, Output Right Reg
No Load Operation, Output Left Reg
No Load Operation, Pass Barrel Shifter Result
YY = Source of Output
XX = Source of Output
CLK latches the instruction into the device.
to be loaded into either, neither or both of the registers. Data
is loaded at the end of the cycle in which the instruction is
executing.
from either of the two registers, the selected output will be valid
during the cycle in which the instruction is executing.
The register file instructions (see Table 4) allow input data
The register file instructions allow the output to be sourced
Operation
Operation