PDSP16515AA0AC Mitel Networks Corporation, PDSP16515AA0AC Datasheet - Page 18

• Manufacturer Part Number: PDSP16515AA0AC
• Description: Stand Alone FFT Processor
• Manufacturer: Mitel Networks Corporation

PDSP16515A
BITS 5:4
These bits define the choice of window operator. If other
windows are needed they must be applied externally. The
fourth option is used to specify the inverse transform, which
does not require the use of a window operator. When 16 x 16
complex transforms are specified by Bits 2:0, only the
rectangular window can be used. The use of any of the other
options will cause the device to enter an internal test mode.
BITS 8:6
These bits define 0%, 50%, or 75% data block overlapping,
and the division factor on the DIS input. Overlapping must not
be specified with 16 x 16 complex transforms.
Two decodes allow the DIS input to be divided by two or four,
when 50% and 75% overlapping is respectively needed.
These options allow the DOS and DIS input pins to be still
supplied from a common source, even though the output rate
must be faster than the input rate. The frequency of this source
would be dictated by the output rate requirement, with the
input rate internally reduced by the correct amount.
Special decodes are provided to support real only transforms
from dual sources, using both the real and auxiliary inputs.
When data is from a single source, and no overlaps are
needed, only the real input should be used. If 50% or 75%
overlaps are needed from a single source of real data, the
device always expects blocks to be simultaneously loaded. An
external FIFO is then needed to supply data to the real inputs
after a delay of one block. Each block is thus loaded twice,
firstly through the Auxiliary inputs and then through the Real
inputs.
BIT 10:9
These bits define a single device system, or one of three
multiple device possibilities. The choice between the first and
second multiple device mode is dependent on the transform
size and the sampling rate needed. The third mode should
only be used when overlapped multiple transforms with less
than 1024 points are to be performed simultaneously. It
changes the LFLG logic and allows sampling rates up to the
system clock rate to be achieved with multiple output
processors.
BIT 11
When this bit is set the PDSP16515A will not generate DAV
until 24 DOS clocks after data was actually valid. In this case
the output tri-state drivers will be enabled at the correct time,
even though the DAV signal was not externally valid. Host
controlled dumping should not be used.
18
BITS
2:0
3
5:4
8:6
10:9
11
12
14:13
15
Table 6. Mode Control Bit Allocations
Dec'
000
001
010
011
100
101
110
111
0
1
00
01
10
11
000
001
010
011
100
101
110
111
00
01
10
11
0
1
0
1
00
01
10
11
0
1
OPTION
16 x 16 COMPLEX
4 x 64 COMPLEX
256 COMPLEX
1024 COMPLEX
8 X 64 REAL
2 X 256 REAL
2 X 1024 REAL
NOT USED
SHIFT 3 PLACES AFTER PASS1
ALWAYS SHIFT 2 PLACES
RECTANGULAR
HAMMING WINDOW
BLACKMAN-HARRIS
INVERSE TRANSFORM
NO OVERLAP
50% OVERLAP
50% OVERLAP AND DIS
75% OVERLAP
75% OVERLAP AND DIS
DUAL SOURCE, NO OVERLAP
DUAL SOURCE, 50% OVERLAP
DUAL SOURCE, 75% OVERLAP
SINGLE DEVICE
N DEVICES, CONCURRENT I/O
N DEVICES, LOAD-TRANS-DUMP
SPECIAL MULTIPLE TRANSFORM
DAV NOT DELAYED
24 CLK DAV DELAY
INEN EDGE ACTIVATED
INEN IS SIMPLE ENABLE
O/P FIRST QUARTER
O/P FIRST HALF
O/P LAST HALF
O/P ALL RESULTS
NORMAL DAV
KEEP DAV ACTIVE TILL INEN
2
4