87C196JQ Intel Corporation, 87C196JQ Datasheet - Page 24

• Manufacturer Part Number: 87C196JQ
• Description: ADVANCED 16-BIT CHMOS MICROCONTROLLER
• Manufacturer: Intel Corporation

87C196KR KQ 87C196JV JT 87C196JR JQ
6 Port2
Writing to these bits will have no effect
7 Port5
24
On the JR-C P2 3 and P2 5 are not bonded out
but are present internally on the device This al-
lows the programmer to write to the port registers
and clear set or read the pin even though it is not
available to the outside world However to main-
tain compatibility with D-step and future devices
it is recommended that the corresponding bits as-
sociated with the removed pins not be used to
conditionally branch in software
should be treated as reserved
On the JR-D unused port logic for these two port
pins has been removed from the device and is
not available to the programmer Corresponding
bits in the port registers have been ‘‘hardwired’’
to provide the following results when read
Register Bits
P2 PIN x
P2 REG x
P2 DIR x
P2 MODE x
On the JR-C P5 1 P5 4 P5 5 P5 6 and P5 7 are
not bonded out but are present internally on the
device This allows the programmer to write to
the port registers and clear set or read the pin
even though it is not available to the outside
world However to maintain compatibility with D-
step and future devices it is recommended that
the corresponding bits associated with the re-
moved pins not be used to conditionally branch in
software These bits should be treated as re-
served
On the JR-D unused port logic for these five port
pins has been removed from the device and is
not available to the programmer Corresponding
bits in the port registers have been ‘‘hardwired’’
to provide the following results when read
(x
(x
(x
(x
e
e
e
e
3 5)
3 5)
3 5)
3 5)
When Read
These bits
1
1
1
0
Writing to these bits will have no effect
8 Port6
Writing to these bits will have no effect
9 8XC196JQ
Register Bits
P5 PIN x
P5 REG x
P5 DIR x
P5 MODE x
P5 MODE x
P5 MODE x
P5 MODE x
On the JR-C P6 2 and P6 3 are not bonded out
but are present internally on the device This al-
lows the programmer to write to the port registers
and clear set or read the pin even though it is not
available to the outside world However to main-
tain compatibility with D-step and future devices
it is recommended that the corresponding bits as-
sociated with the removed pins not be used to
conditionally branch in software
should be treated as reserved
On the JR-D unused port logic for these two port
pins has been removed from the device and is
not available to the programmer Corresponding
bits in the port registers have been ‘‘hardwired’’
to provide the following results when read
Register Bits
P6 PIN x
P6 REG x
P6 DIR x
P6 MODE x
Roll-over Point
8XC196JQ devices are simply 8XC196JR devic-
es with less memory Both the JQ-C and JQ-D
are fabricated from the JR-C and JR-D respect-
fully The difference between JQ and JR devices
is that memory locations beyond the supported
boundaries on the JQ are not tested in produc-
tion and should not be used Any software which
relies upon reading or writing these locations may
not function correctly Following are the support-
ed memory maps for these devices
Internal
(x
(x
(x
(x
(x
(x
(x
e
e
e
e
e
e
e
(x
(x
(x
(x
1 4 5 6 7)
1 4 5 6 7)
1 4 5 6 7)
1 4 6)
5) (EA
5) (EA
7)
e
e
e
e
2 3)
2 3)
2 3)
2 3)
to
e
e
External
0)
1)
When Read
When Read
These bits
1
1
1
0
Memory
1
1
1
0
1
0
1