87C196JQ Intel Corporation, 87C196JQ Datasheet - Page 5

• Manufacturer Part Number: 87C196JQ
• Description: ADVANCED 16-BIT CHMOS MICROCONTROLLER
• Manufacturer: Intel Corporation

PIN DESCRIPTIONS
V
V
V
V
ANGND
XTAL1
XTAL2
P2 7 CLKOUT
RESET
P5 7 BUSWIDTH
NMI
P5 1 INST
EA
P5 0 ALE ADV
CC
SS
REF
PP
Symbol
V
SS
V
SS
Main supply voltage (
Digital circuit ground (0V) There are three V
connected to a single ground plane
Reference for the A D converter (
analog portion of the A D converter and the logic used to read Port 0 Must be
connected for A D and Port 0 to function
Programming voltage for the EPROM parts It should be
programming It is also the timing pin for the return from powerdown circuit
Connect this pin with a 1 F capacitor to V
function is not used V
Reference ground for the A D converter Must be held at nominally the same
potential as V
Input of the oscillator inverter and the internal clock generator
Output of the oscillator inverter
Output of the internal clock generator The frequency is
frequency It has a 50% duty cycle Also LSIO pin
Reset input to the chip Input low for at least 16 state times will reset the chip The
subsequent low to high transition resynchronizes CLKOUT and commences a 10-
state time sequence in which the PSW is cleared bytes are read from 2018H and
201AH loading the CCBs and a jump to location 2080H is executed Input high for
normal operation RESET has an internal pullup
Input for bus width selection If CCR bit 1 is a one and CCR1 bit 2 is a one this pin
dynamically controls the Bus width of the bus cycle in progress If BUSWIDTH is
low an 8-bit cycle occurs If BUSWIDTH is high a 16-bit cycle occurs If CCR bit 1
is ‘‘0’’ and CCR1 bit 2 is ‘‘1’’ all bus cycles are 8-bit if CCR bit 1 is ‘‘1’’ and CCR1
bit 2 is ‘‘0’’ all bus cycles are 16-bit CCR bit 1
illegal Also an LSIO pin when not used as BUSWIDTH
A positive transition causes a non-maskable interrupt vector through memory
location 203EH Used by Intel (GND this pin)
Output high during an external memory read indicates the read is an instruction
fetch INST is valid throughout the bus cycle INST is active only during external
memory fetches during internal EP ROM fetches INST is held low Also LSIO
when not INST
Input for memory select (External Access) EA equal to a high causes memory
accesses to locations 2000H through 5FFFH to be directed to on-chip EPROM
ROM EA equal to a low causes accesses to these locations to be directed to off-
chip memory EA
Mode EA latched at reset
Address Latch Enable or Address Valid output as selected by CCR Both pin
options provide a latch to demultiplex the address from the address data bus
When the pin is ADV it goes inactive (high) at the end of the bus cycle ADV can
be used as a chip select for external memory ALE ADV is active only during
external memory accesses Also LSIO when not used as ALE
SS
e a
a
PP
12 5V causes execution to begin in the Programming
5V)
may be tied to V
Name and Function
87C196KR KQ 87C196JV JT 87C196JR JQ
a
5V) V
CC
REF
SS
SS
and a 1 M
e
is also the supply voltage to the
pins all of which MUST be
‘‘0’’ and CCR1 bit 2
a
resistor to V
12 5V for
the oscillator
e
CC
‘‘0’’ is
If this
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