87C752 Philips Semiconductors, 87C752 Datasheet - Page 7

• Manufacturer Part Number: 87C752
• Description: 80C51 8-bit microcontroller family 2K/64 OTP/ROM/ 5 channel 8 bit A/D/ I2C/ PWM/ low pin count
• Manufacturer: Philips Semiconductors

Philips Semiconductors
I/O Ports
The I/O pins provided by the 83C752 consist of port 0, port 1, and
port 3.
Port 0
Port 0 is a 5-bit bidirectional I/O port and includes alternate functions
on some pins of this port. Pins P0.3 and P0.4 are provided with
internal pullups while the remaining pins (P0.0, P0.1, and P0.2) have
open drain output structures. The alternate functions for port 0 are:
P0.0
P0.1
P0.4
If the alternate functions, I
these pins may be used as I/O ports.
Port 1
Port 1 is an 8-bit bidirectional I/O port whose structure is identical to
the 80C51, but also includes alternate input functions on all pins.
The alternate pin functions for port 1 are:
P1.0-P1.4 - ADC0-ADC4 - A/D converter analog inputs
P1.5 INT0 - external interrupt 0 input
P1.6 INT1 - external interrupt 1 input
P1.7 - T0 - timer 0 external input
If the alternate functions INT0, INT1, or T0 are not being used, these
pins may be used as standard I/O ports. It is necessary to connect
AV
pins as standard I/O pins. When the A/D converter is enabled, the
analog channel connected to the A/D may not be used as a digital
input; however, the remaining analog inputs may be used as digital
inputs. They may not be used as digital outputs. While the A/D is
enabled, the analog inputs are floating.
Port 3
Port 3 is an 8-bit bidirectional I/O port whose structure is identical to
the 80C51. Note that the alternate functions associated with port 3
of the 80C51 have been moved to port 1 of the 83C752 (as
applicable). See Figure 1 for port bit configurations.
1999 Jul 23
80C51 8-bit microcontroller family
2K/64 OTP/ROM, 5 channel 8 bit A/D, I
CC
WRITE TO
and AV
INT. BUS
SCL – the I
SDA – the I
PWM – the PWM output
LATCH
LATCH
READ
READ
PIN
SS
to V
CC
2
2
C bus clock
C bus data
and V
CL
D
2
LATCH
ALTERNATE INPUT
C and PWM, are not being used, then
P1.X
SS
FUNCTION
Q
, respectively, in order to use these
Q
ALTERNATE
FUNCTION
OUTPUT
Figure 1. Port Bit Latches and I/O Buffers
V
DD
INTERNAL
PULL-UP
2
P1.X
PIN
C, PWM, low pin count
7
Counter/Timer Subsystem
The 8XC752 has one counter/timer called timer/counter 0. Its
operation is similar to mode 2 operation on the 80C51, but is
extended to 16 bits with 16 bits of autoload. The controls for this
counter are centralized in a single register called TCON.
A watchdog timer, called Timer I, is for use with the I
In I
bus monitoring of the I
use as a fixed time-base.
Interrupt Subsystem—Fixed Priority
The IP register and the 2-level interrupt system of the 80C51 are
eliminated. The interrupt structure is a seven-source, one-level
interrupt system similar to the 8XC751. Simultaneous interrupt
conditions are resolved by a single-level, fixed priority as follows:
Highest priority:
Lowest priority:
The vector addresses are as follows:
Source
INT0
TF0
INT1
TIMER I
SIO
ADC
PWM
Interrupt Control Registers
The 80C51 interrupt enable register is modified to take into account
the different interrupt sources of the 8XC752.
WRITE TO
2
INT. BUS
C applications, this timer is dedicated to time-generation and
LATCH
LATCH
READ
READ
PIN
Vector Address
Pin INT0
Counter/timer flag 0
Pin INT1
PWM
Timer I
Serial I
ADC
0003H
000BH
0013H
001BH
0023H
002BH
0033H
CL
D
2
LATCH
C. In non-I
ALTERNATE INPUT
P0.X
FUNCTION
2
C
Q
Q
ALTERNATE
FUNCTION
OUTPUT
2
C applications, it is available for
83C752/87C752
Product specification
2
C subsystem.
SU00306
P0.X
PIN