DSP56156 Motorola Inc, DSP56156 Datasheet
DSP56156
Related parts for DSP56156
DSP56156 Summary of contents
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... DSP56156 a cost-effective, high-performance solution for many DSP applications, especially speech coding, digital communications, and cellular base stations. The central processing unit of the DSP56156 is the DSP56100 core processor. Like all DSP56100- based DSPs, the DSP56156 consists of three execution units operating in parallel, allowing up to six operations to be performed during each instruction cycle ...
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... On-chip Harvard architecture permitting simultaneous accesses to program and memories • 2048 16-bit on-chip program RAM and 64 ( 16-bit on-chip program ROM on the DSP56156ROM) • 2048 16-bit on-chip data RAM • External memory expansion with 16-bit address and data buses • ...
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... V power supply Product Documentation This data sheet plus the two manuals listed in Table 1 are required for a complete DSP56156 description and are necessary to properly design with the part. Documentation is available from a local Motorola distributor, a semiconductor sales office, or through a Motorola Litera- ture Distribution Center ...
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... Introduction Documentation Data Sheet Contents Related Documentation Table 2 lists additional documentation relevant to the DSP56156. Table 2 Related Motorola Documentation Topic DSP Family Brochure Development Tools Fractional and Integer Arithmetic Fast Fourier Transforms (FFTs) G.722 Audio Processing Dr. BuB Bulletin Board Third Party Compendium ...
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... Freescale Semiconductor, Inc. Pin Groupings The DSP56156 is available in a 112-pin Ceramic Quad Flat Pack (CQFP) and a 112-pin Plastic Thin Quad Flat Pack (TQFP). The input and output signals are organized into the functional groups indicated in Table 3. Figure 2 illustrates the chip’s pin functions. ...
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... Mode Control Timer/Event On-Chip Counter Emulator (OnCE ) Port Clock and Phase-locked Loop (PLL) On-Chip Codec 112 pins Figure 2 DSP56156 Pin Functions DSP56156 Data Sheet For More Information On This Product, Go to: www.freescale.com H0-H7* HA0-HA2* HR/W* HEN* HREQ* HACK* STD0* SRD0* SCK0* SC00-SC10* STD1* SRD1* ...
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... This pin provides an “early bus start” signal which can be used as address latch and as an “early bus end” signal which can be used by an external bus controller three-stated during hardware reset. DSP56156 Data Sheet Go to: www.freescale.com Pin Descriptions Address and Data Bus Bus Control 7 ...
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... BS 8 Freescale Semiconductor, Inc. BR (Bus Request) — active low output Figure 3 TA Controlled Accesses DSP56156 Data Sheet For More Information On This Product, Go to: www.freescale.com sampled high by the leading edge of T0 sampled low (assert- ed) at the leading edge of the t0 begin- ...
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... When BG is deasserted, the DSP will release the bus as soon as the current transfer is completed. The state of BG may be tested by testing the BS bit in the Bus Control Register ig- nored during hardware reset. DSP56156 Data Sheet Go to: www.freescale.com Pin Descriptions Bus Control 9 ...
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... Freescale Semiconductor, Inc. MODB/IRQB MODC (Mode Select C) — input. This input RESET (Reset) — input. This input is a direct DSP56156 Data Sheet For More Information On This Product, Go to: www.freescale.com (Mode Select B/External In- terrupt Request B) — input. This in- put has two functions: • ...
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... MC68000 family processors. If programmed as a host acknowledge signal, HACK may be used as a data strobe for HI DMA data transfers. If pro- grammed as an MC68000 host interrupt DSP56156 Data Sheet Go to: www.freescale.com Pin Descriptions Interrupt and Mode Control Host Interface 11 ...
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... SRD0-1 (SSI0-1 Receive Data) — input*. SCK0-1 (SSI0-1 Serial Clock) — bidirection- SC10-11 (SSI0-1 Serial Control 1) — bidirec- SC00-01 (SSI0-1 Serial Control 0) — bidirec- DSP56156 Data Sheet For More Information On This Product, Go to: www.freescale.com PC0 and PC5, respectively, when the STD function is not being used. ...
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... This pin should be left floating when the codec is not used. MIC (Microphone) — input. This pin is se- lected as the analog input to the A/D converter when the INS bit is cleared in DSP56156 Data Sheet Go to: www.freescale.com Pin Descriptions OnCE On-Chip Codec 13 ...
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... CLKO (Clock Output) — output. This pin )V . This pin should CCA SXFC (External Filter Capacitor) — This pin DSP56156 Data Sheet For More Information On This Product, Go to: www.freescale.com plies a quiet ground source to the PLL to provide greater frequency stability. (Analog Power) — This pin is the posi- tive analog supply input ...
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... Electrical Characteristics and Timing CAUTION: Exceeding maximum electrical ratings will permanently damage or disable the chip, or impair the chip’s long term reliability. The DSP56156 is fabricated in high density HCMOS with TTL compatible inputs and CMOS compatible outputs. Table 4 Maximum Electrical Ratings (GND = 0 Vdc) Rating ...
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... MGS1 - — MGS1 - — 0. 1.8 — — (See Note 3) — — 500 1 — 0. DSP56156 Data Sheet For More Information On This Product, Go to: www.freescale.com Typ Max Unit 78 1400 k — — 1.414 Vp — 0.707 Vp — 354 mVp — ...
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... Note 2) -50 dBm0 - MHz ÷ 6.5 13 MHz 1 MHz ÷ 13 ÷ Signal in dB DSP56156 Data Sheet Go to: www.freescale.com Electrical Characteristics and Timing A/D and D/A Performance Typ Max Unit (See Note 1) 65 — — — — ...
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... Codec Sampling Rate A/D Section Group Delay D/A Section Group Delay 18 Freescale Semiconductor, Inc. = -40 to +125 TTL Load Min 0.1 78 — — DSP56156 Data Sheet For More Information On This Product, Go to: www.freescale.com Typ Max Unit 2.048 3 MHz 16000 37000 Hz — 0.2 msec — ...
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... TSI - -0.1 OHC — OLC V — — Š must be true. IHC ILC DSP56156 Data Sheet Go to: www.freescale.com DC Electrical Characteristics and Timing Typ Max Unit — — 0 — — — 20 — ...
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... The DSP56156 output levels are measured with the production test machine V ence levels set at 0.8 V and 2.0 V respectively. Clock Operation Timing The system clock to the DSP56156 must be externally supplied to EXTAL as illustrated in Figure 6. Num Characteristics ...
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... CC IHC 0.01 F 0.1 F XFC V SXFC CCS 16 VCO PFD PLL YD3-YD0 GSM 6.5 CODEC DSP56156 Data Sheet Go to: www.freescale.com AC Electrical Characteristics and Timing Clock Operation Timing V IHC 90% Midpoint 10% V ILC 5 Unit MHz Vpp CC GNDS PLLE=1 Fosc 4 PLLE=0 internal phase PH0 at Fosc ...
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... DSP56156 Data Sheet For More Information On This Product, Go to: www.freescale.com 60 MHz Unit Max Min Max 23 — — 600KT — ns — 60T — ns 18T+17 16T ...
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... DSP56156 Data Sheet Go to: www.freescale.com AC Electrical Characteristics and Timing 60 MHz Unit Max Min Max cyc - 27 — cyc - cyc - 27 — 3 cyc - 26 ns cyc-2 12 ...
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... The instruction fetch is visible on the pins only in Mode 2 and Mode 3. RESET 10 D0-D15 A0-A15 PS/DS R/W BS CLKO 13 RESET A0-A15 PS/DS BS R/W 24 Freescale Semiconductor, Inc. 11 Figure 7 Asynchronous Reset Timing 14 Figure 8 Synchronous Reset Timing DSP56156 Data Sheet For More Information On This Product, Go to: www.freescale.com V IHR 12 First Fetch MOTOROLA ...
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... Figure 11 External Level-Sensitive Fast Interrupt Timing MOTOROLA For More Information On This Product, Reset, Stop, Wait, Mode Select, and Interrupt Timing IHM V ILM 17 First Interrupt Instruction Execution General Purpose I/O DSP56156 Data Sheet Go to: www.freescale.com AC Electrical Characteristics and Timing V IHR V IH IRQA V IRQB IL 25 ...
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... Figure 14 Recovery from Stop State Using IRQA Interrupt Service 26 Freescale Semiconductor, Inc. T1, T3 T0, T2 phi1 phi0 DSP56156 Data Sheet For More Information On This Product, Go to: www.freescale.com First Interrupt Instruction Fetch First Instruction Fetch Not IRQA Interrupt Vector First IRQA Interrupt Instruction Fetch MOTOROLA ...
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... DSP56156 Data Sheet Go to: www.freescale.com AC Electrical Characteristics and Timing 60 MHz Unit Max Min Max cyc - 3 8 cyc - 2 ns — 18 cyc — ns — 29 cyc — ...
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... Figure 16 Recovery from Wait/Stop State Using DR Pin — Asynchronous Timing Capacitance Derating The DSP56156 External Bus Timing Specifications are designed and tested at the maximum ca- pacitive load of 50 pF, including stray capacitance. Typically, the drive capability of the Exter- nal Bus pins (A0-A15, D0-D15, PS/DS, RD, BS, WR, R/W) derates linearly per additional capacitance from 250 pF of loading ...
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... Min 2.4 9 4.7 12 4.7 14 18.3 — 13.4 T+3.1 T+12.4 T+3.1 14.3 15.8 11.8 2.6 10.3 2.6 4.5 — 4.5 0 — 1.7 7.1 1.7 2.0 — 2.0 6 — 0 — — 10 2.2 — 1.2 4.2 2.8 — DSP56156 Data Sheet Go to: www.freescale.com AC Electrical Characteristics and Timing External Bus Synchronous Timing 50 MHz 60 MHz Max Min Max 2.4 9 2.4 9 4.7 12 4.7 12 (See Note) 4.7 14 4.7 4 — 9.8 — T+12.4 T+3.1 T+12.4 13.3 10.2 11.8 10.3 2.6 10.3 — 4.5 — 0 — 0 — 7.1 1.7 7.1 — ...
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... NOTE: During Read-Modify-Write instructions and internal instructions, the address lines do not change state. Figure 17 External Bus Synchronous Timing — No Wait States 30 Freescale Semiconductor, Inc Data Out 50 45 Data In DSP56156 Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA ...
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... D0-D15 (Input) Figure 18 External Bus Synchronous Timing – Two Wait States MOTOROLA For More Information On This Product Data Out 45 DSP56156 Data Sheet Go to: www.freescale.com AC Electrical Characteristics and Timing External Bus Synchronous Timing ...
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... V dc ± 10 cyc = Clock cycle = WS = Number of Wait States, Determined by BCR Register ( 31 Freescale Semiconductor, Inc. = -40 to +125 TTL Load instruction cycle = 2 T cycles 2 cyc = 2T WS DSP56156 Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA ...
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... NOTE: During Read-Modify-Write instructions and internal instructions, the address lines do not change state. Figure 19 External Bus Asynchronous Timing MOTOROLA For More Information On This Product Data Out DSP56156 Data Sheet Go to: www.freescale.com AC Electrical Characteristics and Timing External Bus Asynchronous Timing Data In 33 ...
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... CLKO High to Address and Control Bus Active 82 CLKO High to Address and Control Bus Valid NOTES: 1. With no external access from the DSP56156 2. During external read or write access 3. During external read-modify-write access 4. During Stop mode — external bus is released and BG is always low 5 ...
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... BR (Input) BG (Output) BB (I/O) A0-A15 PS/DS R/W D0-D15 Figure 20 Bus Arbitration Timing — Slave Mode — Bus Release MOTOROLA For More Information On This Product DSP56156 Data Sheet Go to: www.freescale.com AC Electrical Characteristics and Timing Bus Arbitration Timing — Slave Mode ...
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... AC Electrical Characteristics and Timing Bus Arbitration Timing — Slave Mode CLKO (Output (Input) BG (Output) BB (I/O) A0-A15 PS/DS R/W Figure 21 Bus Arbitration Timing — Slave Mode — Bus Acquisition 36 Freescale Semiconductor, Inc DSP56156 Data Sheet For More Information On This Product, Go to: www.freescale.com 80 MOTOROLA ...
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... MHz Min Max Min 4.7 12 4.7 9.2 — 6.5 0 — 0 9.2 — 6.5 0 — 0 4 Three-state DSP56156 Data Sheet Go to: www.freescale.com AC Electrical Characteristics and Timing Bus Arbitration Timing — Master Mode 60 MHz Unit Max Min Max 12 4 — 4.5 — ns — 0 — ns — 4.5 — ns — 0 — ...
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... AC Electrical Characteristics and Timing Bus Arbitration Timing — Master Mode CLKO (Output) BR (Output (Input) BB (I/O) A0-A15 PS/DS R/W Figure 23 Bus Arbitration Timing — Master Mode — Bus Release 38 Freescale Semiconductor, Inc. 87 DSP56156 Data Sheet For More Information On This Product, Go to: www.freescale.com MOTOROLA ...
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... DSP56156 Data Sheet Go to: www.freescale.com AC Electrical Characteristics and Timing Host Port Timing 60 MHz Unit Max Min Max 2T+30 ns — 26+t — suh — 26 — — 27 — ns — ...
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... Deassertion for RXL Read, TXL Write (See Note 3) NOTES: 1. “Host Synchronization Delay (tHSDL)” is the time period required for the DSP56156 to sample any external asynchronous input signal, determine whether it is high or low, and synchronize it to the internal clock. 2. See Host Port Considerations. ...
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... HR/W (Input) 106 H0-H7 (Output) Figure 25 Host Interrupt Vector Register (IVR) Read MOTOROLA For More Information On This Product, 100 100 103 101 113 112 107 108 109 Data Valid DSP56156 Data Sheet Go to: www.freescale.com AC Electrical Characteristics and Timing Host Port Timing 102 41 ...
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... Data Valid 120 103 TXH Write 101 102 114 Address Valid 110 104 Data Valid DSP56156 Data Sheet For More Information On This Product, Go to: www.freescale.com 118 RXL Read 115 Address Valid Data Valid 119 TXL Write 115 Address Valid ...
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... For More Information On This Product, 117 102 101 RXH RXL Read Read 108 109 Data Valid 117 101 102 TXH TXL Write Write 105 Data Valid DSP56156 Data Sheet Go to: www.freescale.com AC Electrical Characteristics and Timing Host Port Timing Data Valid Data Valid 43 ...
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... MHz Characteristic Min 100 45 45 — — — — — — — — — DSP56156 Data Sheet For More Information On This Product, Go to: www.freescale.com Case Unit Max — — ns — — ns — — — ...
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... Freescale Semiconductor, Inc. MOTOROLA For More Information On This Product, DSP56156 Data Sheet Go to: www.freescale.com AC Electrical Characteristics and Timing SSI Timing 45 ...
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... DSP56156 Data Sheet For More Information On This Product, Go to: www.freescale.com Case Unit Max — — — — — — ...
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... FSR (Bit) In FSR (Word) In Flags In Figure 30 SSI Receiver Timing MOTOROLA For More Information On This Product, 132 135 136 138 First Bit 142 141 143 DSP56156 Data Sheet Go to: www.freescale.com AC Electrical Characteristics and Timing SSI Timing 137 139 Last Bit 142 144 47 ...
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... In the Normal mode, the output flag state is asserted for the entire frame period. 48 Freescale Semiconductor, Inc. 130 131 132 146 145 147 150 149 155 153 154 156 Figure 31 SSI Transmitter Timing DSP56156 Data Sheet For More Information On This Product, Go to: www.freescale.com 148 150 151 First Bit Last Bit 155 (See Note) MOTOROLA ...
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... MOTOROLA For More Information On This Product TTL Load) L Table 21 Timer Timing 40/50/60 MHz Min 6 0 3.5 5 172 171 Figure 32 Timer Timing DSP56156 Data Sheet Go to: www.freescale.com AC Electrical Characteristics and Timing OnCE Port Timing Unit Max — ns — 20.7 ns — ns — ...
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... TTL Load Table 22 OnCE Port Timing Characteristic (See Note 1) (See Note 1) (See Note 1) (See Note 2) (See Note 2) (See Note 2) (See Note 2) DSP56156 Data Sheet For More Information On This Product, Go to: www.freescale.com 40/50/60 MHz Unit Min Max — 5.2 — ...
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... NOTE: Three-state, external pull-down resistor Figure 35 OnCE Port Data I/O To Status Timing MOTOROLA For More Information On This Product, 183 184 185 194 (Last) (See Note) 193 182 DSP56156 Data Sheet Go to: www.freescale.com AC Electrical Characteristics and Timing OnCE Port Timing ACK (OS1) (ACK) (OS0) 188 51 ...
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... SPKP SPKM GNDA VDIV VREF NOTE: An OVERBAR indicates the signal is asserted when the voltage = ground (active low). Figure 39 Top View of the DSP56156 112-pin Plastic (FC) and Ceramic (FE) Quad Flat Packages 52 Freescale Semiconductor, Inc. Orientation Mark (Top View) DSP56156 Data Sheet For More Information On This Product, Go to: www ...
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... V CC6 H5/PB5 H6/PB6 57 NOTE: An OVERBAR indicates the signal is asserted when the voltage = ground (active low). Figure 40 Bottom View of the DSP56156 112-pin Plastic (FC) and Ceramic (FE) Quad Flat Packages MOTOROLA For More Information On This Product, Orientation Mark (on Top side) (Bottom View) DSP56156 Data Sheet Go to: www ...
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... Table 23 NOTES Tables 23, 24, and 25, OVERBAR indicates the signal is asserted when the voltage = ground (active low). 2. For more information on power and ground, see Table 26 under Design Considerations. 54 Freescale Semiconductor, Inc. DSP56156 General Purpose I/O Pin Identification DSP56156 112-pin DSP56156 General Package ...
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... Freescale Semiconductor, Inc. MOTOROLA For More Information On This Product, DSP56156 Data Sheet Go to: www.freescale.com Pin-out and Package Pin Number 55 ...
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... Pin-out and Package Signal Name DSP56156 Pin Identification by Pin Number Table 24 112-pin Package Signal Name Package Pin # 1 GND4 CC3 GND5 GND6 13 D10 14 D11 15 V CC4 16 D12 17 D13 18 GND7 19 D14 20 D15 ...
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... Freescale Semiconductor, Inc. MOTOROLA For More Information On This Product, DSP56156 Data Sheet Go to: www.freescale.com Pin-out and Package Signal Name 57 ...
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... Pin-out and Package DSP56156 Pin Identification by Signal Name Table 25 112-pin Package Signal Name Pin # 100 A9 102 A10 105 A11 106 A12 107 A13 109 A14 110 A15 30 AUX BIAS 34 BR ...
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... Freescale Semiconductor, Inc. MOTOROLA For More Information On This Product, DSP56156 Data Sheet Go to: www.freescale.com Pin-out and Package 59 ...
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... Pin-out and Package DSP56156 Pin Identification by Signal Name (continued) Table 25 112-pin Package Signal Name Pin # 60 PB2 61 PB3 62 PB4 58 PB5 57 PB6 56 PB7 74 PB8 72 PB9 71 PB10 70 PB11 69 PB12 67 PB13 68 PB14 82 PC0 81 PC1 80 PC2 79 PC3 78 PC4 64 PC5 63 PC6 60 Freescale Semiconductor, Inc. 112-pin Package Signal Name ...
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... CQFP MOTOROLA Freescale Semiconductor, Inc. DSP56156 Data Sheet For More Information On This Product, Go to: www.freescale.com Pin-out and Package 61 ...
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... Datums -L-, -M- and - determined at datum plane -H-. 5. Dimensions S and determined at seating plane -T-. 6. Dimensions A and B define maximum ceramic body dimensions including glass protrusion and mismatch. Figure 41 DSP56156 112-pin Ceramic Quad Flat Pack (CQFP) Mechanical Information 62 Freescale Semiconductor, Inc. TOP ...
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... Freescale Semiconductor, Inc. MOTOROLA For More Information On This Product, DSP56156 Data Sheet Go to: www.freescale.com Pin-out and Package 112 TQFP 63 ...
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... Dimensions A and B do include mold mismatch and are determined at datum plane -H-. 7. Dimension D does not include dambar protrusion. Allowable dambar protrusion shall not cause the D dimension to exceed 0.43 (0.017). DSP56156 112-pin Plastic Thin Quad Flat Pack (TQFP) Mechanical Information Figure 42 64 Freescale Semiconductor, Inc. ...
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... JA Noise Each DSP56156 V with a low-impedance path to +5 volts. Each (at equilibri- D DSP56156 GND pin should likewise be pro- vided with a low-impedance path to ground. The power supply pins drive distinct groups of logic on chip as shown in Table 26. The V passed to GND ground using at least six 0.01 – 0.1 µF bypass capacitors located ei- ther underneath the chip’ ...
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... GND7 V 36 GND8 CC5 23 GNDA V CCA V 59 GND9 CC6 V GND10 76 CC7 V GNDQ0 33 CCQ0 V GNDQ1 96 CCQ1 V 50 GNDS CCS DSP56156 Data Sheet Go to: www.freescale.com Design Considerations Power, Ground, and Noise and CC Ground Pin # 89 95 101 108 104 48 61 ...
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... Table 27 DC Electrical Characteristics Symbol CCA I CCA . Also, all codec pins should be left floating, except VREF which CC DSP56156 Data Sheet For More Information On This Product, Go to: www.freescale.com Typical Unit MHz MHz MHz 91 112 133 ...
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... DSP to Host HC, HREQ, DMA, HF3, HF2, TRDY, TXDE, and RXDF status bits are set or cleared from inside the DSP and read by the host processor (refer to DSP56156 Us- er’s Manual, I/O Interface section, Host/ DMA Interface Programming Model for descriptions of these status bits). The ...
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... HRDF status bits are set or cleared by the host processor side of the interface. These bits are individ- ually synchronized to the DSP clock. (Refer to the DSP56156 User’s Manual, I/O Interface section, Host/DMA In- terface Programming Model for de- scriptions of these status bits.) Bus Operation Figure 43 depicts the operation of the external memory interface with multiple wait states ...
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... AUX Bias 17 dB GNDA VREF 2.0 V 10% (2 VDIV 36 K SPKP 3 POLE 2 ZERO Low Pass SPKM Filter (LPF) VC3-VC0 GNDA V CCA + 0 Analog Decoupling near DSP GNDA DSP56156 Data Sheet Go to: www.freescale.com Design Considerations Analog I/O Considerations MGS1-0 bits modulator + ...
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... C ð 100 nF SPKP Š 500 NC SPKM SPKM (b) Analog Ground and Power planes Figure 46 Ground and Power planes DSP56156 Data Sheet For More Information On This Product, Go to: www.freescale.com 0 < C ð 100 nF SPKP Š 500 SPKM 0 < C ð 100 nF Š 500 (c) 57 ...
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... The DAC outputs (SPKP and SPKM) should be run right next to each other as shown on Figure 48. MOTOROLA For More Information On This Product, BIAS AUX MIC 28 0 Š10 µ DSP56156 Data Sheet Go to: www.freescale.com Design Considerations Analog I/O Considerations CCA pin by short traces. CCA ...
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... Figure 49 presents four options for good power supply connections. 68 Freescale Semiconductor, Inc. BIAS AUX MIC 28 1nF 47 k Copper Fill of unused board space should be connected to the analog ground plane DSP56156 Data Sheet For More Information On This Product, Go to: www.freescale.com 0.25 F MIC IN 5.6 k MOTOROLA ...
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... Ground planes connected with a 10 ¾ resistor as close as possible to the V pin on the codec. Fourth Choice — planes connected at source. Ground planes connected with a 10 ¾ resistor as close as pos- sible to the V CCA DSP56156 Data Sheet Go to: www.freescale.com Design Considerations Analog I/O Considerations 10 BIAS AUX MIC ...
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... Ordering Information Ordering Information Table 28 lists information for ordering parts. Table 28 DSP56156 Ordering Information Supply Package Type Voltage Ceramic Quad Flat 5 V Pack (CQFP Plastic Thin Quad Flat Pack (TQFP) 70 Freescale Semiconductor, Inc. Frequency Pin Count (MHz) 112 112 DSP56156 Data Sheet For More Information On This Product, Go to: www ...
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Freescale Semiconductor, Inc. Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Motorola does not assume any liability arising out of the application or use of any product or ...