IMP16C552-CJ68 IMP Inc, IMP16C552-CJ68 Datasheet - Page 12

• Manufacturer Part Number: IMP16C552-CJ68
• Description: Dual Universal Asynchronous Receiver/Transmitter (UART) with 16-BYTE FIFO & Parallel Printer Port
• Manufacturer: IMP Inc

12
Line Control Register
The system programmer specifies the format
of the asynchronous data communications
exchange and sets the divisor latch access bit
via the line control register (LCR) the
programmer can also read the contents of the
line control register the read capability
simplifies system programming and eliminates
the need for separate storage in system
memory of the line characteristics
Bits 0 and1 : these two bit
number of bits each transmitted or serial
character the encoding of bits 0and 1 is as
follows:
Bit 2: this bit specifies the number of stop bits
transmitted and received in each serial
character if bit 2is a logic 0 0ne stop bit is
generated in the transmitted data if bit 2 is
logic 1 when a 5-bit word length is selected
via bits 0 and1 ,0ne and half stop bits are
generated if bit 2 is a logic 1 when either a
6-7- ,or 8-bit word length is selected .2 stop
bits are generated the receiver checks the fist
stop-bit only regardless of the number of stop
bits selected
Bit3:this bit is the parity enable bit when bits 3
is a logic 1 a parity bit is generated (transmit
data)or checked (receive data )between the
last data word bit and stop bit of the serial
data (the parity bit is used to produce an ever
or odd number of 1’s when the data word bits
and the parity bit are summed
Bit 4:this bit is the even parity selects bit when
bit 3 is a logic 1 and bit 4 is a logic 0 an odd
number of logic 1 ‘s is transmitted or checked
in the data word bits and parity bit when bit 3
is a logic 1 and bit 4 is a logic 1 and even
number of logic 1s is transmitted or checked
in the data word bits and parity bit
Bit 5: this bit is the stick parity bit when bits 3
and 5 are logic 1 the parity bit is transmitted
and detected by the receiver in the opposite
state indicated by bit 4 is bit 5 is zero stick
parity is disabled
Bit 1
0
0
1
1
Bit 0
0
1
0
1
Character length
5bits
6bits
7bits
8bits
s specify the
408-432-9100/www.impweb.com
Bit 6:thus bit is the break control bit it causes
a break control condition to be transmitted to
the receiving UART when bit 6 set to a logic 1
the serial output (SOUT) is forced to the
spacing (logic0) state and remains there until
bit 6 is set to a logic 0 this bit acts only on
SOUT pin and has no effect on transmitted
logic this feature enable the CPU to alert a
terminal
system if the following sequence is followed
no erroneous characters will be transmission
because of break.
1 .Load an all 0s pad character in response to THRE
2. set break after the next THER
3. wait for the transmitted to be idle (TEMT=1) and clear
break when normal transmitted has to be restored
During the break the transmitted can be the
used as a character time to accurately
establish the break duration
Bit 7:this bit the divisor latch access bit (DLAB)
it must be set high (logic1)to access the
divisor latches of the baud rate generator
during a read or write operation it must be
set low (logic 0) to access the receiver buffer
the transmitter holding register or the interrupt
enable register
Programmable baud rate generator
The
generator that is capable of taking any clock
input from DC to 8 0 MHz and dividing it by
any divisor from 1 to 2
frequency of the baud generator is 16 x the
baud rate two 8-bit latches store the divisor in
a 16-bit binary format. These Divisor Latches
must be loaded during initialization to ensure
proper operation of the Baud Rate Generator.
Upon loading either of the Divisor Latches, a
16-bit Baud counter is immediately loaded.
This prevents long counts on initial load.
Table III. IV and V illustrate the use of the
Baud Rate Generator with three different
driving frequencies. Table III references to a
1.8430 MHz clock, table IV to a 3.070 MHz
clock, and table V to a 8 MHz clock. For baud
rates of 38400 and below, the error obtained
is minimal. The accuracy of the desired baud
rate is dependent on the crystal frequency
chosen. Using a divisor of zero is not
recommended. In no case should the data
rate be greater than 512K baud.
UART contains a programmable baud
in
IMP16C552
a
IMP16C552
computer
communications
–1 the output
© 2002 IMP, Inc.