IMP16C552-CJ68 IMP Inc, IMP16C552-CJ68 Datasheet - Page 14

• Manufacturer Part Number: IMP16C552-CJ68
• Description: Dual Universal Asynchronous Receiver/Transmitter (UART) with 16-BYTE FIFO & Parallel Printer Port
• Manufacturer: IMP Inc

14
Table V- Baud Rate using 8.0 MHz Clock
Line Status Register
This register provides status information to the
CPU concerning the data transfer. Table II
shows the contents of the Line Status Register.
Description of each bit follows:
Bit 0: This bit is the receiver Data Ready
(RDR) indicator. Bit 0 is set to a logic 1
whenever a complete incoming character has
been received and transferred into the
Receive Buffer Register of the FIFO. Bit 0 is
reset to a logic 0 by reading all of the data in
the Receive Buffer Register
mode ) or the RCVR FIFO (for FIFO mode).
Bit 1: This bit is the Overrun Error (OE)
indicator. Bit 1 indicates that data in the
Receiver Buffer Register was not read by the
CPU
transferred into the Receiver Buffer Register,
thereby destroying the previous character.
The OE indicator is set to a logic 1 upon
detection of an overrun condition and reset
whenever the CPU reads the contents of the
Line Status Register. If the FIFO mode data
continues to fill FIFO beyond the trigger level.
Desired
128000
256000
19200
38400
56000
Baud
134.5
Rate
1200
1800
2000
2400
3600
4800
7200
9600
110
150
300
600
50
75
before
the
Divisor Used
To Generate
16x clock
next
10000
6667
4545
3717
3333
1667
833
417
277
250
208
139
104
69
52
26
13
9
4
2
character
(for character
408-432-9100/www.impweb.com
was
Difference Between
Desired and Actual
Percent Error
0.005
0.010
0.013
0.010
0.020
0.040
0.080
0.080
1.160
0.080
1.160
0.644
1.160
1.160
1.160
0.790
2.344
2.344
an overrun error will occur only after the FIFO
is full and the next character has been
completely received in the shift register. An
OE is indicated as soon as it happens . The
character in the shift register is overwritten,
but nothing will transferred to the FIFO.
Bit 2: This bit is the Parity Error (PE) indicator.
Bit 2 indicates that the received data character
does not have the correct even or odd parity,
as selected by the even-parity-select bit. The
PE is set to a logic 1 upon detection of a parity
error and is reset to a logic 0 whenever the
CPU reads the contents of the Line Status
Register. In the FIFO mode this error is
associated with the particular character in the
FIFO and revealed to the CPU when the
associated character is the top of the FIFO.
Bit 3: This bit is the Framing Error (FE)
indicator. Bit 3 indicates that the received
character did not have a valid Stop bit. Bit 3 is
set to a logic 1 whenever the Stop bit following
the last data bit or parity bit is detected as a
logic 0 bit (Spacing level). The FE indicator is
reset whenever the CPU reads the contents of
the Line Status Register. In the FIFO mode
–
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IMP16C552
IMP16C552
© 2002 IMP, Inc.