LM3207TL-2.53 National Semiconductor, LM3207TL-2.53 Datasheet - Page 21

• Manufacturer Part Number: LM3207TL-2.53
• Description: LM3207 650mA Miniature, Adjustable, Step-Down DC-DC Converter for RF Power Amplifiers with Integrated Vref LDO; Package: MICRO SMD; No of Pins: 9; Qty per Container: 250; Container: Reel
• Manufacturer: National Semiconductor

BOARD LAYOUT FLOW
1.
2.
3.
4.
Minimize C1, PV
be as wide and short as possible. This is most important.
Minimize L1, C2, SW and PGND loop. These traces also
should be wide and short. This is the second priority.
Above layout patterns should be placed on the
component side of the PCB to minimize parasitic
inductance and resistance due to via-holes. It may be a
good idea that the SW to L1 path is routed between C2
(+) and C2(-) land patterns. If vias are used in these large
current paths, multiple via-holes should be used if
possible.
Connect C1(-), C2(-) and PGND with wide GND pattern.
This pattern should be short, so C1(-), C2(-), and PGND
should be as close as possible. Then connect to a PCB
IN
, and PGND loop. These traces should
FIGURE 5. Evaluation Board Layout
21
5.
6.
7.
Note: The evaluation board shown in Figure 5 for the LM3207 was designed
common GND pattern with as many via-holes as
possible.
SGND should not connect directly to PGND. Connecting
these pins under the device should be avoided. (If
possible, connect SGND to the common port of C1(-), C2
(-) and PGND.)
FB line should be protected from noise. It is a good idea
to use an inner GND layer (if available) as a shield.
The LDO Cap C7 (C
PA as possible and as far away from the switcher to
suppress high frequency switch noises.
with these considerations, and it shows good performance. However
some aspects have not been optimized because of limitations due to
evaluation-specific requirements. Please refer questions to a Nation-
al representative.
LDO
) should be placed as close to the
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