LM3543MX-H National Semiconductor, LM3543MX-H Datasheet - Page 10

• Manufacturer Part Number: LM3543MX-H
• Description: LM3543 Triple Port USB Power Distribution Switch and Over-Current Protection; Package: SOIC NARROW; No of Pins: 16; Qty per Container: 2500; Container: Reel
• Manufacturer: National Semiconductor

www.national.com
POWER SUPPLY FILTERING
A sizable capacitor should be connected to the input of the
LM3543 to ensure the voltage drop on this node is less than
330 mV during a heavy-load hot-plug event. A 33 µF, 16V
tantalum capacitor is recommended. The input supply should
be further bypassed with a 0.01 µF - 0.1 µF ceramic capacitor,
placed close to the device. The ceramic capacitor reduces
ringing on the supply that can occur when a short is present
at the output of a port.
EXTENDING THE FAULT FLAG DELAY
While the 7 ms (typical) internal delay in reporting flag condi-
tions is adequate for most applications, the delay can be
extended by connecting external RC filters to the FLAG pins,
as shown in
POWER DISSIPATION AND JUNCTION TEMPERATURE
A few simple calculations will allow a designer to calculate the
approximate operating temperature of the LM3543 for a given
application. The large currents possible through the low re-
sistance power MOSFET combined with the high thermal
resistance of the SOIC package, in relation to power pack-
ages, make this estimate an important design step.
Begin the estimate by determining R
erating temperature using the graphs in the Typical Perfor-
FIGURE 5. Typical Circuit for Lengthening the Internal
Figure
5.
Flag Delay
FIGURE 6. Self-Powered Hub Connections and Per-Port Voltage Drop
101258 Version 5 Revision 6
ON
at the expected op-
10125828
Print Date/Time: 2010/02/04 15:48:33
10
mance Characteristics section of this datasheet. Next,
calculate the power dissipation through the switch with
tion
Note: Equation for power dissipation neglects portion that
comes from LM3543 quiescent current because this value will
almost always be insignificant.
Using this figure, determine the junction temperature with
Equation
Where:
θ
Temperature (°C).
Compare the calculated temperature with the expected tem-
perature used to estimate R
match, re-estimate R
temperature and repeat the calculations. Reiterate as neces-
sary.
PCB LAYOUT CONSIDERATIONS
In order to meet the USB requirements for voltage drop, droop
and EMI, each component used in this circuit must be evalu-
ated for its contribution to the circuit performance. These
principles are illustrated in
rules and guidelines are recommended
1.
2.
3.
4.
JA
= SOIC Thermal Resistance: 130°C/W and T
1.
Place the switch as close to the USB connector as
possible. Keep all V
use at least 50-mil, 1 ounce copper for all V
Solder plating the traces will reduce the trace resistance.
Avoid vias as much as possible. If vias are used, use
multiple vias in parallel and/or make them as large as
possible.
Place the output capacitor and ferrite beads as close to
the USB connector as possible.
If ferrite beads are used, use wires with minimum
resistance and large solder pads to minimize connection
resistance.
2.
T
J
PD = R
= PD * θ
ON
bus
using a more appropriate operating
Figure
ON
traces as short as possible and
JA
* I
ON
+ T
DS
. If they do not reasonably
6. The following PCB layout
2
A
.
bus
A
10125827
= Ambient
traces.
Equa-
(1)
(2)