IDT72V205L20TF IDT, Integrated Device Technology Inc, IDT72V205L20TF Datasheet - Page 12

• Manufacturer Part Number: IDT72V205L20TF
• Description: IC FIFO SYNC 16KX9 20NS 64QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V205L20TF

• Function: Asynchronous
• Memory Size: 144K (16K x 9)
• Access Time: 20ns
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-STQFP
• Configuration: Dual
• Density: 4.5Kb
• Access Time (max): 12ns
• Word Size: 18b
• Organization: 256x18
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: STQFP
• Clock Freq (max): 50MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 30mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Rate: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 72V205L20TF

NOTES:
1. t
2. Select this mode by setting (FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during Reset.
NOTES:
1. When t
2. The first word is available the cycle after EF goes HIGH, always.
3. Select this mode by setting (FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during Reset.
IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
Q
Q
D
edge of WCLK and the rising edge of RCLK is less than t
Latency Timing applies only at the Empty Boundary (EF = LOW).
SKEW1
0
WCLK
WCLK
0
0
RCLK
RCLK
- Q
WEN
REN
- D
WEN
- Q
REN
OE
OE
EF
EF
17
17
17
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. If the time between the rising
SKEW1
minimum specification, t
t
t
ENS
ENS
t
DS
Figure 8. First Data Word Latency with Single Register-Buffered EF
Figure 7. Read Cycle Timing with Single Register-Buffered EF
FRL
t
D
OLZ
0
(maximum) = t
(first valid write)
t
t
ENH
CLKH
t
SKEW1
t
REF
t
A
CLK
t
OE
SKEW1
t
OLZ
+ t
, then EF may not change state until the next RCLK edge.
t
SKEW1
CLK
t
FRL
NO OPERATION
. When t
(1)
t
SKEW1
D
1
t
REF
t
CLKL
SKEW1
t
ENS
(1)
12
< minimum specification, t
TM
t
OE
VALID DATA
D
t
A
2
EF EF
EF EF (IDT Standard Mode)
FRL
t
EF EF
EF EF (IDT Standard Mode)
REF
(maximum) = either 2*t
t
OHZ
D
COMMERCIAL AND INDUSTRIAL
0
D
t
A
3
CLK
TEMPERATURE RANGES
+ t
SKEW1
OCTOBER 22, 2008
or t
CLK
D
4294 drw 08
+ t
1
D
4294 drw 07
SKEW1
4
. The