IDT72V205L20TF IDT, Integrated Device Technology Inc, IDT72V205L20TF Datasheet - Page 20

• Manufacturer Part Number: IDT72V205L20TF
• Description: IC FIFO SYNC 16KX9 20NS 64QFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr

Specifications of IDT72V205L20TF

• Function: Asynchronous
• Memory Size: 144K (16K x 9)
• Access Time: 20ns
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 64-STQFP
• Configuration: Dual
• Density: 4.5Kb
• Access Time (max): 12ns
• Word Size: 18b
• Organization: 256x18
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: STQFP
• Clock Freq (max): 50MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Supply Current: 30mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Rate: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 72V205L20TF

NOTES:
1. t
2. LD = HIGH.
3. Select this mode by setting (FL, RXI, WXI) = (0,1,0) or (1,1,0) during Reset.
NOTES:
1. t
2. LD = HIGH.
3. Select this mode by setting (FL, RXI, WXI) = (0,1,0) or (1,1,0) during Reset.
Q
D
IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
D
WCLK
RCLK
WCLK
0
0
0
WEN
edge of RCLK and the rising edge of WCLK is less than tSKEW1, then the FF deassertion time may be delayed an extra WCLK cycle.
edge of RCLK and the rising edge of WCLK is less than t
RCLK
REN
SKEW1
SKEW1
WEN
-
- Q
- D
REN
D
FF
OE
FF
17
17
17
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH after one WCLK cycle plus t
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH after one WCLK cycle plus t
LOW
DATA IN OUTPUT REGISTER
t
ENS
NO WRITE
t
SKEW1
1
Figure 25. Write Cycle Timing with Double Register-Buffered FF FF FF FF FF (IDT Standard Mode)
t
(1)
SKEW1
t
CLKH
Figure 24. Double Register-Buffered Full Flag Timing (IDT Standard Mode)
t
ENH
(1)
t
A
1
t
CLK
t
SKEW1
CLKL
. then the FF deassertion may be delayed an extra WCLK cycle.
2
t
WFF
2
t
DS
t
WFF
20
TM
Wd
t
WFF
DATA READ
DATA IN VALID
t
ENS
t
DS
t
ENS
NO WRITE
t
SKEW1
t
ENH
(1)
t
t
ENH
DH
t
A
t
1
WFF
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
WFF
RFF
NO OPERATION
. If the time between the rising
. If the time between the rising
OCTOBER 22, 2008
NEXT DATA READ
DATA WRITE
2
t
WFF
4294 drw 25
4294 drw 24
t
DS