AN1176 STMicroelectronics, AN1176 Datasheet - Page 4

• Manufacturer Part Number: AN1176
• Description: 68HC11/PSD813F1 DESIGN GUIDE
• Manufacturer: STMicroelectronics

A Common Solution
For ISP, some 68HC11 designers will use the boot-loader feature of the 68HC11 UART to
download executable code into SRAM (either the small on-board 68HC11 SRAM or an external
SRAM chip) then the 68HC11 jumps to that SRAM to execute the remainder of the download
process for programming the main flash memory. This can be a cumbersome and error prone
exercise, which is difficult to debug and is vulnerable to power outages.
An Better, Integrated Solution
A more robust choice for the type of alternate memory for ISP loader code is Flash or EEPROM.
Figure 2 shows a two-chip solution using an FLASH PSD. This system has ample main
flash memory, EEPROM for the alternate memory, and some SRAM. All three of these
memories can operate independently and concurrently; meaning the MCU can operate from one
memory while erasing/writing the other. The system has programmable logic, expanded I/O, and
design security. This two-chip solution is 100% ISP.
The ISP method described so far requires MCU participation to exercise a communication
channel to implement a download to the main flash memory. The PSD813F also offers an
alternative ISP method that uses a built-in IEEE-1149.1 JTAG interface, and requires no MCU
participation. This means that a completely blank PSD can be soldered into place, and the entire
chip can be programmed in-system using ST's FlashLINK
development software ($99 USD for both, see www.st.com/psm). No 68HC11 firmware needs to
be written, just plug in the FlashLINK
configuration. This is a powerful new feature of the PSD813F that allows immediate
development of application code in your lab, smart manufacturing techniques, and easy field
updates.
Let’s take a quick look inside the FLASH PSD813F1, as shown in Figure 3. You can see
the three independent memory arrays, which are selected on a segment basis when the proper
MCU address is decoded in the Decode PLD. The page register participates in memory
decoding, which greatly simplifies paging. The MCU address, data, and control signals have
access to just about everything inside the chip, including the general purpose CPLD. The CPLD
has 16 macrocells, and 24 special latches for input signals. All 16 macrocells and 24 input
Page
Com puter
2
Host
Figure 2 – Embedded flash system capable of ISP (2 devices)
Com m unication
Channel
Em bedded System
68HC11
TM
cable and begin programming memory, logic, and
* 1 2 8 K B yte s F la sh
* 3 2 K B yte s E E P R O M
* 2 K B yte s S R A M
* P ro g ra m m a b le L o g ic
* I/O
TM
JTAG cable and PSDsoft
PSD813F1
JT A G
S yste m
I/O