DS2751 Maxim Integrated Products, DS2751 Datasheet - Page 18

• Manufacturer Part Number: DS2751
• Description: Multichemistry Fuel Garge
• Manufacturer: Maxim Integrated Products

I/O SIGNALING
The 1-Wire bus requires strict signaling protocols to insure data integrity. The four protocols used by the
DS2751 are: the initialization sequence (reset pulse followed by presence pulse), Write 0, Write 1, and
Read Data. All of these types of signaling except the presence pulse are initiated by the bus master.
The initialization sequence required to begin any communication with the DS2751 is shown in Figure 15.
A presence pulse following a reset pulse indicates the DS2751 is ready to accept a net address command.
The bus master transmits (Tx) a reset pulse for t
receive mode (Rx). The 1-Wire bus line is then pulled high by the pullup resistor. After detecting the
rising edge on the DQ pin, the DS2751 waits for t
Figure 15. 1-WIRE INITIALIZATION SEQUENCE
WRITE TIME SLOTS
A write time slot is initiated when the bus master pulls the 1-Wire bus from a logic high (inactive) level to
a logic low level. There are two types of write time slots: Write 1 and Write 0. All write time slots must
be t
DS2751 samples the 1-Wire bus line between 15
sampled, a Write 1 occurs. If the line is low when sampled, a Write 0 occurs (see Figure 16). For the bus
master to generate a Write 1 time slot, the bus line must be pulled low and then released, allowing the line
to be pulled high within 15
slot, the bus line must be pulled low and held low for the duration of the write time slot.
READ TIME SLOTS
A read time slot is initiated when the bus master pulls the 1-Wire bus line from a logic high level to a
logic low level. The bus master must keep the bus line low for at least 1
DS2751 to present valid data. The bus master can then sample the data t
read time slot. By the end of the read time slot, the DS2751 releases the bus line and allows it to be pulled
high by the external pullup resistor. All read time slots must be t
1
m
s minimum recovery time, t
SLOT
DQ
(60
m
s to 120
LINE TYPE LEGEND:
m
s) in duration with a 1
t
m
RSTL
BUS MASTER ACTIVE LOW
BOTH BUS MASTER AND
DS2751 ACTIVE LOW
s after the start of the write time slot. For the host to generate a Write 0 time
REC
, between cycles. See Figure 16 for more information.
t
PDH
m
RSTL
18 of 19
PDH
m
s minimum recovery time, t
s and 60
. The bus master then releases the line and goes into
and then transmits the Presence Pulse for t
t
PDL
m
s after the line falls. If the line is high when
DS2751 ACTIVE LOW
RESISTOR PULLUP
t
RSTH
SLOT
(60ms to 120ms) in duration with a
m
s and then release it to allow the
RDV
(15
REC
m
s) from the start of the
, between cycles. The
PACK+
PACK–
PDL
.