DS90C383 National Semiconductor, DS90C383 Datasheet - Page 4

• Manufacturer Part Number: DS90C383
• Description: +3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-65 MHz/ +3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link-65 MHz
• Manufacturer: National Semiconductor

www.national.com
Symbol
TRANSMITTER SUPPLY CURRENT
ICCTG
ICCTZ
RECEIVER SUPPLY CURRENT
ICCRW
ICCRG
ICCRZ
LLHT
LHLT
TCIT
TCCS
TPPos0
TPPos1
TPPos2
TPPos3
TPPos4
TPPos5
TPPos6
TCIP
TCIH
TCIL
TSTC
THTC
TCCD
TPLLS
TPDD
Symbol
Over recommended operating supply and temperature ranges unless otherwise specified.
Electrical Characteristics
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
Note 2: Typical values are given for V
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise speci-
fied (except V
Note 4: V
Transmitter Switching Characteristics
Over recommended operating supply and −40˚C to +85˚C ranges unless otherwise specified
Transmitter Supply Current
16 Grayscale
Transmitter Supply Current
Power Down
Receiver Supply Current
Worst Case
Receiver Supply Current,
16 Grayscale
Receiver Supply Current
Power Down
OS
OD
LVDS Low-to-High Transition Time (Figure 3 )
LVDS High-to-Low Transition Time (Figure 3 )
TxCLK IN Transition Time (Figure 5 )
TxOUT Channel-to-Channel Skew (Figure 6 )
Transmitter Output Pulse Position for Bit 0 (Figure 17 )
Transmitter Output Pulse Position for Bit 1
Transmitter Output Pulse Position for Bit 2
Transmitter Output Pulse Position for Bit 3
Transmitter Output Pulse Position for Bit 4
Transmitter Output Pulse Position for Bit 5
Transmitter Output Pulse Position for Bit 6
TxCLK IN Period (Figure 7)
TxCLK IN High Time (Figure 7)
TxCLK IN Low Time (Figure 7)
TxIN Setup to TxCLK IN (Figure 7 )
TxIN Hold to TxCLK IN (Figure 7 )
TxCLK IN to TxCLK OUT Delay 25˚C, V
Transmitter Phase Lock Loop Set (Figure 11 )
Transmitter Power Down Delay (Figure 15 )
previously referred as V
and V
OD
Parameter
).
CM
CC
.
= 3.3V and T
(Continued)
A
= +25C.
R
C
16 Grayscale Pattern
(Figures 2, 3 ) , T
−40˚C to +85˚C
Power Down = Low
Driver Outputs in TRI-STATE
Power Down Mode
C
Worst Case Pattern
(Figures 1, 4 ) , T
−40˚C to +85˚C
C
16 Grayscale Pattern
(Figures 2, 4 ) , T
−40˚C to +85˚C
Power Down = Low
Receiver Outputs Stay Low during
Power Down Mode
Parameter
L
L
L
L
= 100 ,
= 5 pF,
= 8 pF,
= 8 pF,
CC
= 3.3V (Figure 9 )
Conditions
4
A
A
A
=
=
=
f = 32.5 MHz
f = 37.5 MHz
f = 65 MHz
f = 32.5 MHz
f = 37.5 MHz
f = 65 MHz
f = 32.5 MHz
f = 37.5 MHz
f = 65 MHz
®
under
f = 65 MHz
f = 65 MHz
Min
0.35T
0.35T
−0.4
10.6
12.8
Min
1.8
4.0
6.2
8.4
2.5
3.0
15
0
Typ
23
28
31
10
49
53
78
28
30
43
10
0.75
0.75
13.2
0.5T
0.5T
Typ
250
2.2
4.4
6.6
8.8
3.7
11
0
T
Max
105
0.65T
0.65T
35
40
45
55
65
70
45
47
60
55
Max
11.3
13.5
100
2.5
4.7
6.9
9.1
1.5
1.5
0.3
5.5
50
10
5
Units
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
µA
µA
ms
ns
ns
ns
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns