DS90CR218 National Semiconductor, DS90CR218 Datasheet - Page 8

• Manufacturer Part Number: DS90CR218
• Description: +3.3V Rising Edge Data Strobe LVDS 21-Bit Channel Link Receiver - 75 MHz
• Manufacturer: National Semiconductor

www.national.com
RxIN+
RxIN−
RxOUT
RxCLK IN+
RxCLK IN−
RxCLK OUT
PWR DWN
V
GND
PLL V
PLL GND
LVDS V
LVDS GND
AC Timing Diagrams
C — Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max
Tppos — Transmitter output pulse position (min and max)
RSKM
Cable Skew — typically 10 ps–40 ps per foot, media dependent
Note 6: Cycle-to-cycle jitter is less than 250 ps at 75MHz
Note 7: ISI is dependent on interconnect length; may be zero
DS90CR218 Pin Description—Channel Link Receiver
Note 8: These receivers have input failsafe bias circuitry to guarantee a stable receiver output for floating or terminated receiver inputs. Under these conditions
receiver inputs will be in a HIGH state. If a clock signal is present, outputs will all be HIGH; if the clock input is also floating/terminated outputs will remain in the last
valid state. A floating/terminated clock input will result in a LOW clock output.
CC
Pin Name
CC
CC
Cable Skew (type, length) + Source Clock Jitter (cycle to cycle) (Note 6) + ISI (Inter-symbol interference) (Note 7)
I/O
O
O
1
I
I
I
I
I
I
I
I
I
I
FIGURE 9. Receiver LVDS Input Skew Margin (DS90CR217/DS90CR218)
No.
21
3
3
1
1
1
1
4
5
1
2
1
3
Positive LVDS differential data inputs. (Note 8)
Negative LVDS differential data inputs. (Note 8)
TTL level data outputs.
Positive LVDS differential clock input.
Negative LVDS differential clock input.
TTL level clock output. The rising edge acts as data strobe. Pin name RxCLK OUT.
TTL level input. When asserted (low input) the receiver outputs are low.
Power supply pins for TTL outputs.
Ground pins for TTL outputs.
Power supply for PLL.
Ground pin for PLL.
Power supply pin for LVDS inputs.
Ground pins for LVDS inputs.
(Continued)
8
Description
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