DS90CR484 National Semiconductor, DS90CR484 Datasheet - Page 11

no-image

DS90CR484

Manufacturer Part Number
DS90CR484
Description
48-Bit LVDS Channel Link Serializer/Deserializer
Manufacturer
National Semiconductor
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DS90CR484AVJD
Manufacturer:
NS
Quantity:
1 000
Part Number:
DS90CR484AVJD/NOPB
Manufacturer:
NSC
Quantity:
90
Part Number:
DS90CR484AVJD/NOPB
Manufacturer:
Texas Instruments
Quantity:
10 000
Part Number:
DS90CR484AVJDX/NOPB
Manufacturer:
Texas Instruments
Quantity:
10 000
Part Number:
DS90CR484VJD
Manufacturer:
NS
Quantity:
853
Part Number:
DS90CR484VJD
Manufacturer:
NS/国半
Quantity:
20 000
Part Number:
DS90CR484VJD/NOPB
Manufacturer:
NS
Quantity:
277
Part Number:
DS90CR484VJD/NOPB
Manufacturer:
Texas Instruments
Quantity:
10 000
Part Number:
DS90CR484VJDX/NOPB
Manufacturer:
Texas Instruments
Quantity:
10 000
Note 9: Inputs default to “low” when left open due to internal pull-down resistor.
DS90CR483 Pin Description—Channel Link Transmitter
TxIN
TxOUTP
TxOUTM
TxCLKIN
TxCLKP
TxCLKM
PD
PLLSEL
PRE
DS_OPT
V
GND
PLLV
PLLGND
LVDSV
LVDSGND
NC
CC
Pin Name
CC
CC
I/O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
No.
48
8
8
1
1
1
1
1
1
1
8
5
2
3
3
4
4
TTL level input. (Note 9).
Positive LVDS differential data output.
Negative LVDS differential data output.
TTL level clock input. The rising edge acts as data strobe.
Positive LVDS differential clock output.
Negative LVDS differential clock output.
TTL level input. Assertion (low input) tri-states the outputs, ensuring low
current at power down. (Note 9).
PLL range select. This pin must be tied to V
reserved for future use. (Note 9)
Pre-emphasis “level” select. Pre-emphasis is active when input is tied to
V
Pre-emphasis level (See Applications Information Section). For normal
LVDS drive level (No Pre-emphasis) leave this pin open (do not tie to
ground).
Cable Deskew performed when TTL level input is low. No TxIN data is
sampled during Deskew. To perform Deskew function, input must be held
low for a minimum of 4 clock cycles. The Deskew operation is normally
conducted after the TX and RX PLLs have locked. It should also be
conducted after a system reset, or a reconfiguration event. It must be
peformed at least once when DESKEW is enabled. (Note 9)
Power supply pins for TTL inputs and digital circuitry.
Ground pins for TTL inputs and digital circuitry.
Power supply pin for PLL circuitry.
Ground pins for PLL circuitry.
Power supply pin for LVDS outputs.
Ground pins for LVDS outputs.
No Connect. Make NO Connection to these pins - leave open.
CC
through external pull-up resistor. Resistor value determines
11
Description
CC
. NC or tied to Ground is
www.national.com

Related parts for DS90CR484