DS90CR484 National Semiconductor, DS90CR484 Datasheet - Page 12

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DS90CR484

Manufacturer Part Number
DS90CR484
Description
48-Bit LVDS Channel Link Serializer/Deserializer
Manufacturer
National Semiconductor
Datasheet

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Note 10: These receivers have input fail-safe bias circuitry to guarantee a stable receiver output for floating or terminated receiver inputs. Under test conditions re-
ceiver inputs will be in a HIGH state. If the cable inter-connect are disconnected which results in floating/terminated inputs, the outputs will remain in the last valid
state.
DS90CR484 Pin Description—Channel Link Receiver
RxINP
RxINM
RxOUT
RxCLKP
RxCLKM
RxCLKOUT
PLLSEL
DESKEW
PD
V
GND
PLLV
PLLGND
LVDSV
LVDSGND
NC
CC
Pin Name
CC
CC
I/O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
No.
48
8
8
1
1
1
1
1
1
8
8
1
2
2
3
6
Positive LVDS differential data inputs.
Negative LVDS differential data inputs.
TTL level data outputs. In PowerDown (PD = Low) mode, receiver outputs
are forced to a Low state.
Positive LVDS differential clock input.
Negative LVDS differential clock input.
TTL level clock output. The rising edge acts as data strobe.
PLL range select. This pin must be tied to V
reserved for future use. (Note 9)
Deskew / Oversampling “on/off” select. When using the Deskew /
Oversample feature this pin must be tied to V
disables this feature. (Note 9)
TTL level input. When asserted (low input) the receiver outputs are Low.
(Note 9)
Power supply pins for TTL outputs and digital circuitry.
Ground pins for TTL outputs and digital circuitry.
Power supply for PLL circuitry.
Ground pin for PLL circuitry.
Power supply pin for LVDS inputs.
Ground pins for LVDS inputs.
No Connect. Make NO Connection to these pins - leave open.
12
Description
CC
CC
. NC or tied to Ground is
. Tieing this pin to ground

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