DS92LV1021 National Semiconductor, DS92LV1021 Datasheet - Page 3

• Manufacturer Part Number: DS92LV1021
• Description: 16-40 MHz 10 Bit Bus LVDS Serializer and Deserializer
• Manufacturer: National Semiconductor

Data Transfer
RCLK pin is the reference to data on the ROUT0-ROUT9
pins. The polarity of the RCLK edge is controlled by the
RCLK_R/F input.
ROUT(0-9), LOCK and RCLK outputs will drive a minimum
of three CMOS input gates (15 pF load) with 40 MHz clock.
Resynchronization
The Deserializer LOCK pin driven low indicates that the De-
serializer PLL is locked to the embedded clock edge. If the
Deserializer loses lock, the LOCK output will go high and the
outputs (including RCLK) will be TRI-STATE.
The LOCK pin must be monitored by the system to detect a
loss of synchronization and the system must arrange to
pulse the Serializer SYNC1 or SYNC2 pin to resynchronize.
There are multiple approaches possible. One recommenda-
tion is to provide a feedback loop using the LOCK pin itself to
control the sync request of the Serializer (SYNC1 or
SYNC2). Otherwise, LOCK pin needs to be monitored and
when it is a high, the system needs to ensure that one or
both of the Serializer SYNC inputs area asserted for at least
1024 cycles of TCLK. A minimum of 1024 sync patterns are
needed to resynchronize. Dual SYNC pins are provided for
multiple control in a multi-drop application.
Powerdown
The Powerdown state is a low power sleep mode that the
Serializer and Deserializer may use to reduce power when
NSID
DS92LV1021TMSA
DS92LV1210TMSA
(Continued)
Order Numbers
Deserializer
3
Serializer
Function
there is no data to be transferred. Powerdown is entered
when PWRDN and REN are driven low on the Deserializer,
and when the PWRDN is driven low on the Serializer. In
Powerdown, the PLL is stopped and the outputs go into TRI-
STATE, disabling load current and also reducing supply cur-
rent to the milliamp range. To exit Powerdown, PWRDN is
driven high.
Both the Serializer and Deserializer must reinitialize and re-
synchronize before data can be transferred. Initialization of
the Serializer takes 1024 TCLK cycles. The Deserializer will
initialize and assert LOCK high until it is locked to the Bus
LVDS clock.
TRI-STATE
For the Serializer, TRI-STATE is entered when the DEN pin
is driven low. This will TRI-STATE both driver output pins
(DO+ and DO−). When DEN is driven high the serializer will
return to the previous state as long as all other control pins
remain static (SYNC1, SYNC2, PWRDN, TCLK_R/F).
For the Deserializer, TRI-STATE is entered when the REN
pin is driven low. This will TRI-STATE the receiver output
pins (ROUT0–ROUT9), LOCK and RCLK.
MSA28
Package
MSA28
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