AN2007 Motorola / Freescale Semiconductor, AN2007 Datasheet - Page 6

• Manufacturer Part Number: AN2007
• Description: Evaluating ColdFire in a 68K Target System: MC68340 Gateway Reference Design
• Manufacturer: Motorola / Freescale Semiconductor

Address (A1–A23) and data lines (D0–31) from the MCF5206 Microprocessor connect directly to the
ASIC. On board power-up, the physical transfer size of data through the DMA can be set. Data can be
transferred in words (16 bit) or long words (32 bit).
The chip select for the dual DMA controller is generated by chip select 5 (CS5) on the MCF5206. Chip
selects 2,3 and 6 on the MCF5206 are connected to chip selects 1,2 and 3 on the MC68340 target hardware
and re-routed via the routing PCB. Timing differences on the chip select lines due to different processor
speeds and peripheral access times must be considered and accounted for in the ColdFire initialisation code,
usually by the addition of programmable wait states. To make use of the full debug capabilities of the
MCF5206, a 26-way BDM connector has been included on the Gateway Reference Board. A designer can
download, debug, step and trace their code, and program the flash
1.2.1.4 Pull-Up Resistors, LED’s and Miscellaneous Connections
The green surface mount LED, D2, is connected to the 5V supply and current limited by the 1K resistor, R1.
This indicates that power is applied to the Gateway board. The red LED, D1 indicates that a RESET signal
has been asserted either by the reset controller, the MC68340 target hardware or by an external device
through the BDM target connector. GPIO activity on the debug DDATA port pins is indicated using three
different colored LED’s – D3, D4 and D5 (Red, yellow and green respectively). These LEDs may also be
driven by customer firmware, if required.
All critical active low control signals must be pulled high to avoid false signals and erroneous switching.
These key control signals and their appropriate pull-up resistance values are shown at the bottom of Figure 4
and Figure 10.
1.2.2 Additional 8 Bit I/O Interface for The MCF5206
The schematic in Figure 4 shows how the additional 8-bit I/O port is created using a Motorola
MC74AC646DW. This device provides multiplexed transmission of data directly from the data bus to and
from the MCF5206. The MC74AC646DW has internal registers which give the port an additional feature
in that data can be stored and clocked out of the port. This feature can be activated by pulling JP6 or JP7
high.
Chip select 7 from the MCF5206 will enable the additional port. The Read/Write (R/W) line from the
MCF5206 determines whether the port is an input or an output and is connected to the output enable
direction (DIR) pin. If this line is driven low the port will act as an output for a write and conversely a high
will configure the port as an input for a read.
In order to activate, or address the 8-bit I/O interface, the active low chip enable pin on the MC74AC646
chip must be driven low. Chip select 7 from the MCF5206 Microprocessor carries out this function. Since
the control signal for chip enable is active low, pull-up resistor R39 is required for correct circuit operation
at power up.
The MC74AC646DW uses the same clock signal as the MCF5206 ensuring that the additional I/O port
operates synchronously.
1.2.3 MC68340 PGA Connector/PGA Footprint
The diagram in Figure 6 shows the connections from the MC68340 Plastic Grid Array (PGA) to four 36-way
SMT connectors. For reference, the diagram in Figure 7 shows the footprint (bottom view) of the MC68340
Microprocessor (Each line on Figure 6 is labeled to its reference on the footprint of the MC68340 in
Figure 7).
MC68340 PGA–MCF5206FT, Gateway Reference Design
6
/SIZE pin
logic 0
logic 1
jumper in 3 / 2 position
jumper in 2 / 1 position
MC68340 Gateway Reference Design
long-word size
word size